Senior SOC Verification Engineer - Networking - Bengaluru, India
Originally posted 6 October 2026 by the employer.
Verify Smart Network Interface Cards and Data Processing Units.
About the role
As a Senior SOC Verification Engineer, you will be responsible for the verification of the design, architecture, and micro-architecture of Smart Network Interface Cards (Smart-NICs) and Data Processing Units (DPUs).
What you'll do
- Integrate all components for defined project milestones and deliver models to teams for further verification at cluster/sub-system/SOC/emulation levels.
- Develop verification infrastructure and automated flows to streamline the integration of multiple IPs.
- Apply advanced verification methodologies like SV-UVM and utilize scripting languages such as Python and Perl.
- Collaborate with the design team to understand architecture and work with Quality Assurance engineers to achieve excellent test coverage and improve hardware quality.
- Coordinate with internal and external teams across different time zones.
What you'll need
- BS or MS in EEE or ECE with 4+ years of experience in design verification.
- Good understanding of Logic Design and Architecture.
- Strong coding skills in SystemVerilog, scripting languages (Perl/Python), and C++.
- Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).
- Exposure to Cluster/Sub-system/Fullchip/SOC level verification environments.
Skills: SOC Verification Engineer, Smart Network Interface Cards, DPUs, pre-silicon, emulation, post-silicon, SV-UVM, python, perl
This role has been open 0 days — well below the 61-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1203
|
Median days open
61 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1203 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 79 | 1203 |
| Open roles in the wider Digital Design & Verification family | 237 | 3179 · 113 employers |
| Median days open | 60 d | 61 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: SOC Verification Engineer, Smart Network Interface Cards, DPUs, pre-silicon, emulation, post-silicon, SV-UVM, python, perl
Who's hiring in this category
- AMD · 104 open roles · median 47 d
- Qualcomm · 102 open roles · median 45 d
- NVIDIA (this employer) · 75 open roles · median 61 d
- Synopsys · 70 open roles · median 29 d
- SiFive · 56 open roles · median 60 d
- Cadence Design Systems · 52 open roles · median 113 d
How we counted: 1203 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 7 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.