ASIC Senior Test Engineer, Annapurna Silicon Operations - Taipei City, TWN, Taiwan
Amazon
Taipei City, TWN, Taiwan
Full-time
1 hour ago
Verification, Validation & Test
Originally posted 6 October 2026 by the employer.
About the role
This role involves developing and debugging test solutions for silicon used in machine learning accelerator servers, focusing on extremely low DPPM product-lines.
What you'll do
- Develop hardware for probe, final test, system-level test, and singulated die testing.
- Design non-standard hardware like FPGAs and HBMs to interface with dies under test.
- Debug systemic yield issues at all inserts, minimizing power delivery, thermal, and contact footprint impacts.
- Direct OSATs on Test cell qualification and release.
- Develop test collateral for each insert and move coverage between inserts based on yield data, cost of test, and downstream effects.
- Perform RMA deep dives to identify test coverage gaps and System-SLT-ATE correlation.
What you'll need
- Background in classic ATE platforms.
- Experience with server management and customer run-time software.
- Familiarity with virtualized machines and specific microcontrollers.
- Experience with hardware development for probe, final test, system-level test, and singulated die testing.
- Ability to direct OSATs on Test cell qualification and release.
- Experience with systemic yield debug and test collateral development.
Market context
This role has been open 0 days — well below the 25-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
510
|
Median days open
25 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (510 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 510 |
| Open roles in the wider Silicon Validation & Test family | 12 | 2199 · 110 employers |
| Median days open | 5 d | 25 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Teradyne · 61 open roles · median 18 d
- Infineon Technologies · 38 open roles · median 33 d
- Renesas Electronics · 34 open roles · median 34 d
- Micron Technology · 29 open roles · median 29 d
- AMD · 26 open roles · median 33 d
- Qualcomm · 25 open roles · median 20 d
How we counted: 510 open Silicon Test Engineering (DFT Test) roles from 74 employers tracked in the SemiconductorJobs index, counted 6 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.