Senior SoC Design Verification Engineer

Build and scale SystemVerilog/UVM environments verifying UCIe, PCIe, CXL, DDR, and HBM subsystems for AI accelerators.

Originally posted 6 August 2026 by the employer.

About the role

As a Senior SoC Design Verification Engineer at Mueon, you will lead verification of AI accelerators and supporting silicon across compute, memory, and die-to-die subsystems. You will drive environments from architecture through silicon bring-up, focusing on reusable testbenches, gate-level debug, and chiplet-based systems.

What you'll do

• Own verification of complex SoC subsystems from architecture review through first silicon.
• Develop reusable SystemVerilog/UVM verification environments, verification plans, functional coverage models, scoreboards, assertions, and self-checking testbenches.
• Integrate and customize Verification IP (VIP) for interfaces including AXI, APB, UCIe, PCIe, CXL, DDR, HBM, Ethernet, and JTAG.
• Lead gate-level simulation (GLS), SDF timing simulation, UPF-aware simulation, and regression debug to ensure silicon readiness.
• Develop scalable UVM Register Abstraction Layer (RAL) infrastructure for CSR verification across large SoCs.
• Drive verification closure through functional coverage, code coverage, assertion coverage, and regression health metrics, while supporting post-silicon bring-up.

What you'll need

• B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
• 7+ years of experience verifying complex ASIC or SoC designs.
• Expert-level experience with SystemVerilog, UVM, and reusable verification methodology.
• Experience developing and maintaining large SoC verification environments, including UVM components, scoreboards, assertions, sequences, and functional coverage.
• Strong experience with gate-level simulation, SDF timing simulation, waveform analysis, regression management, and silicon correlation.
• Experience integrating commercial Verification IP (VIP) and verifying complex bus protocols, as well as experience with UVM Register Abstraction Layer (RAL).
• Python, Perl, Tcl, or equivalent scripting experience for automation and regression infrastructure, alongside industry standard EDA simulation and debug tools.

Nice to have

• 10+ years of experience verifying complex ASIC or SoC designs.
• Experience verifying AI accelerators, GPUs, CPUs, networking ASICs, or large compute SoCs.
• Experience with ARM-based compute subsystems or heterogeneous processor architectures.
• Experience verifying UCIe, PCIe, CXL, AXI, APB, DDR, HBM, Ethernet, JTAG, or other high-speed interfaces.
• Experience with low-power verification, UPF-aware simulation, and power management verification.
• Experience with DFT, DFx, JTAG, scan, and debug infrastructure.
• Experience with emulation, FPGA prototyping, or hardware-assisted verification.
• Experience supporting gate-level signoff, post-silicon validation, and hardware/software co-debug.

Skills: SystemVerilog, UVM, functional coverage, gate-level simulation, VIP

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