Senior Silicon Design Engineer - MY, Penang, Malaysia
Originally posted 21 September 2026 by the employer. Relisted by the employer on 1 October 2026.
This role involves working with RISC-V, PCIe, and DDR4/5.
About the role
This role is for a Senior Silicon Design Engineer focused on front-end silicon design and RTL integration within the AECG ASIC/Custom silicon team. You will contribute to architecture/product definition through early involvement in the product life-cycle, focusing on processor based sub-systems, Serial Standard interfaces, and Memory controllers.
What you'll do
- Convert chip specification to RTL using internal and external IPs.
- Plan and deliver IP level RTL, and implement front-end RTL integration.
- Optimize the design to meet power, performance, area, and timing requirements.
- Write easily readable and synthesizable Verilog RTL.
- Run unit level testing and create assertions for coverage analysis.
- Create block level design documentation and participate in post silicon functional and performance debug and tuning.
What you'll need
- Experience in ASIC/SoC front-end design methodologies with RTL (Verilog and VHDL based).
- Fluency in design and verification languages such as VHDL, Verilog, and System Verilog.
- Proficiency in scripting with TCL, shell script, Perl, and Python.
- Experience with Spyglass for lint and CDC checks.
- Experience in synthesis, LEC flow, and identifying/implementing complex ECO in netlist.
- Experience defining and debugging SDC timing constraints.
Nice to have
- Hands on experience in RTL coding, including IP RTL integration.
- Strong understanding of SOC clocking, reset, boot, and power management flows, and low power design techniques.
- Expertise with quality checks like CDC, Lint, VCLP, LEC.
- Experience in RISC-V, NOC, DMA, bus interfaces (APB, AHB, AXI, OBI).
- Experience in IPs like PCIe and DDR4/5.
- Experience in packet processing, wireless protocols, and base station protocols (CPRI, JESD, Uplink/Downlink).
- Knowledge about system level flows and interaction with Firmware and Software.
Skills: RTL design, Verilog, VHDL, front-end design, IP integration
This role has been open 10 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
980
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (980 roles · 100 employers) |
|---|---|---|
| Open roles in this specialty | 64 | 980 |
| Open roles in the wider Digital Design & Verification family | 251 | 3112 · 115 employers |
| Median days open | 43 d | 61 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL design, Verilog, VHDL, front-end design, IP integration
Who's hiring in this category
- Qualcomm · 147 open roles · median 55 d
- Synopsys · 67 open roles · median 24 d
- AMD (this employer) · 62 open roles · median 43 d
- NXP Semiconductors · 51 open roles · median 70 d
- Analog Devices · 46 open roles · median 37 d
- NVIDIA · 46 open roles · median 55 d
How we counted: 980 open Digital/RTL Design (RTL Design) roles from 100 employers tracked in the SemiconductorJobs index, counted 1 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.