Senior RTL Design Engineer with Memory controllers - Hyderabad-Sattva, India
Originally posted 15 September 2026 by the employer.
This role focuses on the design and validation of AMD’s DDR IPs.
About the role
This role focuses on planning, building, and executing the design and validation of new and existing features for AMD’s DDR IPs and custom IPs. This involves collaborating with cross-functional teams to design and integrate DDR memory controller calibration solutions, including RTL logic, firmware routines, and algorithmic flows.
What you'll do
- Design and implement robust firmware solutions for DDR memory controller calibration across various DDR standards.
- Develop and refine calibration algorithms to ensure reliable memory initialization and operation under varying process, voltage, and temperature (PVT) conditions.
- Create and execute validation plans to verify the correctness and performance of calibration firmware, algorithms, and custom IPs.
- Perform system-level bring-up and debug activities to identify and resolve issues related to memory training and stability.
- Work closely with silicon design, verification, and system engineering teams to align calibration firmware with hardware capabilities and system requirements.
- Stay updated with emerging DDR technologies and calibration techniques, proposing and implementing innovative solutions.
What you'll need
- 5+ years of relevant experience in digital design and RTL design in Verilog/SystemVerilog.
- Knowledge of system-level architecture, including buses like AXI/AHB and bridges.
- Experience with circuit timing/STA and practical experience with tools.
- Working knowledge of C.
- Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards.
- Experience with implementing DRAM/memory controller initialization code and memory subsystem/DDR PHYs training/calibration software.
- Experience with version control systems such as Perforce, ICManage, or Git.
Nice to have
- Embedded experience.
- Familiarity with industry standard lab tools such as high speed scope, compliance packages, or logic analyzers.
This role has been open 19 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
968
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (968 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 64 | 968 |
| Open roles in the wider Digital Design & Verification family | 254 | 3109 · 114 employers |
| Median days open | 46 d | 62 d (−16 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 139 open roles · median 59 d
- Synopsys · 68 open roles · median 25 d
- AMD (this employer) · 64 open roles · median 45 d
- NXP Semiconductors · 47 open roles · median 81 d
- Analog Devices · 45 open roles · median 40 d
- NVIDIA · 45 open roles · median 59 d
How we counted: 968 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.