Senior R&D Engineer – AI-Driven Layout Synthesis, PCells & Design Optimization - US-CA-Calabasas, United States
$129,450 - $215,740 USD yearly
Originally posted 25 September 2026 by the employer.
About the role
The successful candidate will contribute to intelligent design automation workflows spanning layout synthesis, simulation-driven optimization, surrogate modeling, and AI-assisted design generation.
What you'll do
- Develop advanced PCells, Python-based cells, and automated layout generation capabilities for RFIC, microwave, and analog components.
- Design and implement layout automation solutions including geometry generation, placement, routing, symmetry enforcement, design-rule-aware synthesis, and EM-aware design flows.
- Integrate layout automation with circuit and EM simulation environments for automated design optimization, parameter exploration, and design-space analysis.
- Develop intelligent optimization frameworks leveraging machine learning, surrogate modeling, Bayesian optimization, and reinforcement learning techniques.
- Build scalable software solutions in Python and C++ that support AI-assisted semiconductor design workflows.
- Collaborate with RFIC designers, modeling experts, and software engineers to deliver production-quality EDA capabilities.
What you'll need
- MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, or related discipline.
- Strong hands-on experience in RFIC, analog, microwave, or mixed-signal design.
- Deep expertise in layout automation, parameterized layout generation, and PCell development.
- Strong understanding of semiconductor layout methodologies, design rules, physical verification, and EM-aware design practices.
- Experience developing software using Python and/or C++.
- Strong understanding of computational geometry, algorithms, and software architecture.
- Experience with circuit simulation, optimization workflows, and semiconductor design automation tools.
- Proven problem-solving and analytical skills to translate complex engineering workflows into scalable automation solutions.
Nice to have
- Experience with RFIC passive and active component design including inductors, transformers, transmission lines, filters, matching networks, mixers, and power amplifiers.
- Experience with machine learning frameworks such as PyTorch, TensorFlow, or scikit-learn.
- Knowledge of surrogate modeling, design-space exploration, Bayesian optimization, and reinforcement learning.
- Familiarity with ADS, Cadence Virtuoso, EM simulation tools, or related EDA platforms.
- Experience building AI-assisted engineering applications and intelligent automation workflows.
- Experience working in Agile software development environments.
Skills: AI-Driven Layout Synthesis, PCells, layout automation, machine learning, design optimization
This role has been open 14 days — well below the 31-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · AI EDA Design
|
Open roles in category
61
|
Median days open
31 d
|
Median salary
$193k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Keysight Technologies | All employers we track in this specialty (61 roles · 24 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 61 |
| Open roles in the wider Physical Implementation family | 37 | 1473 · 107 employers |
| Median days open | 10 d | 31 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $193k |
Skills observed across this category: AI-Driven Layout Synthesis, PCells, layout automation, machine learning, design optimization
Who's hiring in this category
- NXP Semiconductors · 12 open roles · median 58 d
- Keysight Technologies (this employer) · 7 open roles · median 10 d
- NVIDIA · 7 open roles · median 30 d
- Cadence Design Systems · 6 open roles · median 47 d
- Altera · 3 open roles · median 2 d
- Qualcomm · 3 open roles · median 47 d
How we counted: 61 open EDA/CAD Engineering (AI EDA Design) roles from 24 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.