$80,000 - $200,000 USD yearly
Validate performance and reliability for Trusted Control/Compute Unit (TCU) and BMC systems.
Originally posted 28 August 2026 by the employer.
About the role
The Senior QA Engineer – Performance & Reliability leads performance characterization and reliability validation for the Secure TCU System against data center standards. The scope covers test design, execution, workload bottleneck analysis, and deep-dive root cause investigation across TCU and BMC environments.
What you'll do
- Design and execute test plans for performance benchmarking, stress testing, longevity/endurance testing, and thermal/power characterization of TCU/BMC systems.
- Analyze system behavior under heavy workloads to identify performance bottlenecks in throughput, latency, and resource utilization (CPU, Memory, PCIe).
- Conduct Mean Time Between Failures (MTBF) prediction, long-duration stability tests, and error injection campaigns to validate system robustness.
- Lead deep-dive root cause investigations of performance degradation and reliability failures using oscilloscopes, logic analyzers, and firmware traces.
- Work directly with firmware and hardware engineers to reproduce bugs, analyze crash dumps, and verify fixes.
- Develop and maintain automated performance testing frameworks and reporting dashboards to track regression metrics over time.
What you'll need
- 5+ years of experience in embedded system testing with a focus on performance verification and reliability engineering.
- Deep understanding of TCU, BMC, HMC, RoT (Root of Trust), Secure Boot, TPM, HSM, PCIe (Gen4/5), DDR memory, and networking protocols.
- Proficiency with performance profiling tools, traffic generators, and benchmarks (e.g., SPEC, IOzone, iperf), along with thermal and power measurement tools.
- Strong scripting skills in Python for test automation and data analysis.
- Strong Linux/Unix skills, including kernel tuning, system monitoring, and log analysis.
- Experience with CI/CD pipelines (Jenkins, GitLab CI) and version control (Git).
- BS/MS degree in Computer Science, Electrical Engineering, or a related field.
Nice to have
- Familiarity with C/C++ for code analysis.
- Experience with AI-driven log analysis or anomaly detection tools to predict reliability issues.
- Background in validation of high-speed interfaces (PCIe, CXL) and memory subsystems (DDR5/LPDDR5).
- Experience with data center server architecture and thermal management.
- Knowledge of industry reliability standards (e.g., Telcordia, JEDEC).
Skills: Performance Benchmarking, Reliability Validation, BMC, Root Cause Analysis, Python, MTBF
More semiconductor jobs: Silicon validation jobs
First seen in our index 0 days ago, well below the 42-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
461
|
Median days since first seen
42 d
|
Category median salary (all employers)
$167k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Axiado | All employers we track in this specialty (461 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 461 |
| Open roles in the wider Silicon Validation & Test family | 4 | 2436 · 120 employers |
| Median days since first seen | 0 d | 42 d (+42 d vs this employer) |
| Median salary (USD postings) | n/a | $167k |
Skills observed across this category: Performance Benchmarking, Reliability Validation, BMC, Root Cause Analysis, Python, MTBF
Who's hiring in this category
- AMD · 61 open roles · median 43 d
- Qualcomm · 43 open roles · median 40 d
- Micron Technology · 30 open roles · median 49 d
- Apple · 27 open roles · median 20 d
- NVIDIA · 27 open roles · median 42 d
- Microchip Technology · 22 open roles · median 89 d
How we counted: 461 open Post-Silicon Validation (Silicon Validation) roles from 67 employers tracked in the SemiconductorJobs index, counted 12 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Silicon Validation & Test family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.