Senior Principal Test Engineer - San Jose, California, United States
$205,000 USD yearly
Originally posted 1 October 2026 by the employer.
Astera Labs provides purpose-built connectivity solutions that integrate CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies.
About the role
As a Senior Principal Test Engineer, you will serve as a technical authority for test engineering across complex mixed-signal silicon and high-speed connectivity products. This role is central to delivering reliable, scalable connectivity for rack-scale AI infrastructure by defining and executing test strategies.
What you'll do
- Define and own comprehensive test strategies, specifications, and plans from product definition through high-volume production.
- Establish coverage, quality, yield, test-time, and cost objectives, and drive measurable improvements.
- Partner with design and product engineering teams to identify testability requirements and make effective design-for-test tradeoffs.
- Architect tester solutions and guide development of Tester HW design to meet specific product roadmaps.
- Apply understanding of physical-layer behavior to investigate failures, interpret lab and production data, and resolve complex performance issues.
- Lead root-cause analysis and yield improvement using protocol analyzers, oscilloscopes, manufacturing data, and structured failure analysis.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 12–20 years of experience in Test engineering or Product Engineering from development through high-volume manufacturing.
- Strong experience developing custom test solutions for high-speed, mixed-signal products for high volume manufacturing.
- Working knowledge of high-speed protocols and physical-layer behavior, including PCIe, Ethernet, DDR, NVMe, or USB.
- Experience with Test SW development, production debug, and test-time optimization.
- Proven experience developing and designing custom Test Hardware for PCBA High volume manufacturing.
Nice to have
- Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
- Experience with Electrical HW board design on complex Test HW implementation.
- Strong knowledge of DFT techniques such as SCAN, MBIST, SerDes, and functional test, along with control interfaces such as I2C, I3C, SPI, MDIO, and JTAG.
- Proficiency in C/C++ or Python for ATE programming, data processing, and test automation; familiarity with databases and yield analytics.
- Proficient in Mandarin Chinese.
This role has been open 0 days — well below the 23-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
496
|
Median days open
23 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (496 roles · 73 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 496 |
| Open roles in the wider Silicon Validation & Test family | 20 | 2176 · 110 employers |
| Median days open | 31 d | 23 d (+8 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Teradyne · 58 open roles · median 13 d
- Infineon Technologies · 40 open roles · median 34 d
- Renesas Electronics · 34 open roles · median 29 d
- AMD · 27 open roles · median 28 d
- Micron Technology · 27 open roles · median 30 d
- Qualcomm · 25 open roles · median 15 d
How we counted: 496 open Silicon Test Engineering (DFT Test) roles from 73 employers tracked in the SemiconductorJobs index, counted 1 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.