Senior Principal Software Engineer - Accelerated Verification IP - San Jose, United States
$154,000 - $286,000 USD yearly
Originally posted 15 July 2026 by the employer.
About the role
You will design, develop, and maintain AVIP and Virtual Bridge components spanning feature development, emulation performance, and validation.
What you'll do
- Design and implement protocol functionality in PCIe AVIP and Virtual Bridge components. - Develop and debug BFMs, transactors, and associated software interfaces. - Ensure correctness, performance, and scalability across emulation and acceleration flows. - Participate in feature bring-up, regression, and release activities. - Support customer issues, reproduce problems, and deliver fixes related to PCIe and CXL. - Collaborate with cross-functional teams, controller/PHY teams, and emulation platform teams.
What you'll need
- BS with a minimum of 10 years of experience, MS with a minimum of 7 years of experience, or PhD with a minimum of 5 years of experience. - Strong fundamentals in digital design, computer architecture, and system-level verification. - Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C++. - Understanding of standard interconnect or IO protocols such as PCIe, CXL, or NVMe. - Debugging skills using waveforms, logs, and protocol analyzers. - Ability to work across hardware and software boundaries.
Nice to have
- Familiarity with emulation, acceleration, or hybrid verification flows.
Skills: PCIe, CXL, emulation, SystemVerilog, high-performance verification
This role has been open 215 days — well above the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 50 | 1268 |
| Open roles in the wider Digital Design & Verification family | 121 | 3346 · 116 employers |
| Median days open | 131 d | 67 d (+64 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: PCIe, CXL, emulation, SystemVerilog, high-performance verification
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems (this employer) · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.