Senior Principal Model Bring-up Engineer
$208,000 USD yearly
Bring up open-weight LLM architectures on SambaNova's RDU dataflow accelerators.
Originally posted 29 October 2026 by the employer.
About the role
You will bring new open-weight LLMs, including dense, mixture-of-experts, and hybrid Mamba/attention architectures, up on SambaNova’s RDU dataflow accelerators and into production serving. Focus areas include model adaptation, multi-chip mapping, compilation, numerical validation, and building inference features as shared modules.
What you'll do
- Bring up new LLM architectures end to end, including model adaptation, checkpoint conversion, multi-chip/multi-host mapping, compilation, numerical validation, and production serving with latency and throughput metrics.
- Build shared inference feature modules including continuous batching over a paged KV pool, prompt caching, chunked and incremental prefill, dynamic tensor shapes, speculative decoding (EAGLE-3, drafters, MTP), FP8/FP4, and tensor and expert parallelism.
- Debug cross-functional issues across the model, compiler, and hardware boundaries, landing fixes in shared components.
What you'll need
- B.S. in Computer Science, Electrical Engineering, or related field with 8+ years of industry experience in ML systems, inference, or compiler engineering.
- Strong Python and PyTorch internals experience, plus familiarity with C++.
- Deep transformer-inference knowledge, including KV caching, GQA and sliding window attention, MoE routing, prefill vs decode, batching, and speculative decoding.
- Hands-on experience with accelerator bring-up, ML compilers (MLIR, XLA, TVM, Triton, torch-mlir), or inference engines (vLLM, SGLang, TensorRT-LLM).
- Rigor in numerical debugging and comfort working with Bazel, Slurm, and large monorepos.
Nice to have
- M.S. or Ph.D. in Computer Science, Electrical Engineering, or related field.
- Experience with dataflow or spatial compilers, kernel DSLs, and open-source inference or compiler contributions.
- Experience with FP8 and FP4 inference, Mamba and SSMs, or expert parallelism.
- Experience with multi-agent AI engineering workflows.
More semiconductor jobs: Silicon validation jobs · Austin jobs
This role has been open 0 days — well below the 72-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
119
|
Median days open
72 d
|
Category median salary (all employers)
$190k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | SambaNova | All employers we track in this specialty (119 roles · 31 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 119 |
| Open roles in the wider Silicon Validation & Test family | 5 | 2312 · 112 employers |
| Median days open | 1 d | 72 d (−71 d vs this employer) |
| Median salary (USD postings) | — | $190k |
Who's hiring in this category
- Qualcomm · 18 open roles · median 42 d
- AMD · 16 open roles · median 77 d
- NVIDIA · 12 open roles · median 80 d
- Graphcore · 10 open roles · median 134 d
- Arm Holdings · 7 open roles · median 1 d
- Micron Technology · 6 open roles · median 206 d
How we counted: 119 open Post-Silicon Validation (Design Verification) roles from 31 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.