Senior Principal Engineering Program Manager - San Jose, California, United States
$205,000 - $250,000 USD yearly
Originally posted 22 April 2026 by the employer.
About the role
Astera Labs is looking for a Senior Principal Engineering Program Manager to lead end-to-end execution of advanced-node ASIC products from concept through production. The position holds direct accountability for delivering revenue-critical silicon on time, on spec, and at scale.
What you'll do
- Own full ASIC lifecycle execution across architecture, RTL, verification, physical design, tapeout, validation, customer sampling, qualification, and RTM. - Serve as the single point of ownership for assigned ASIC programs, driving schedules, budgets, resources, and risk management. - Lead cross-functional engineering teams across design, validation, product, test, firmware, software, and operations. - Resolve complex pre-silicon and post-silicon issues through technical judgment. - Manage scope, schedule, and cost trade-offs while communicating status and alignment to executives and stakeholders.
What you'll need
- BS or MS in Electrical, Electronics, or Computer Engineering. - 10+ years of ASIC product development experience in a semiconductor environment. - Hands-on experience in RTL, DSP, or Physical Design with a strong understanding of ASIC development flows. - Experience delivering ASICs in advanced nodes (<10nm). - Demonstrated experience leading in a matrixed environment using MS Project, Jira, Atlassian tools, and Scrum/WBS methodologies.
Nice to have
- 5 or more years of experience as an ASIC Program Manager. - Experience with PCIe, memory, or high-speed data communication ASICs.
Skills: ASIC products, full ASIC lifecycle, RTL, physical design, advanced nodes
This role has been open 185 days — well above the 51-day median for Technical Program Management roles.
Technical Program Management · SOC Architecture
|
Open roles in category
177
|
Median days open
51 d
|
Median salary
$220k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (177 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 177 |
| Median days open | 76 d | 51 d (+25 d vs this employer) |
| Median salary (USD postings) | — | $220k |
Skills observed across this category: ASIC products, full ASIC lifecycle, RTL, physical design, advanced nodes
Who's hiring in this category
- Qualcomm · 25 open roles · median 54 d
- AMD · 21 open roles · median 29 d
- NVIDIA · 20 open roles · median 40 d
- Synopsys · 15 open roles · median 44 d
- Arm Holdings · 10 open roles · median 91 d
- NXP Semiconductors · 7 open roles · median 34 d
How we counted: 177 open Technical Program Management (SOC Architecture) roles from 48 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.