Senior Principal Engineer, Network Modeling Lead - San Jose, California, United States
$207,000 - $230,000 USD yearly
Originally posted 30 July 2026 by the employer.
Scorpio Scale-Up Fabric
About the role
As a Fabric Modeling and Analysis Engineer, you will own the performance models that shape the Scorpio Scale-Up Fabric by quantifying bandwidth, latency, and throughput ceilings under real AI/ML workloads. Your transaction-level and cycle-approximate models will evaluate architectural concepts ahead of tape-out across scaling GPU clusters.
What you'll do
- Design, implement, and maintain features in AI/ML system simulators and fabric models, covering collective communication, transport, topology, congestion, routing, buffering, scheduling, and traffic management. - Improve simulator fidelity, scalability, debuggability, and runtime performance across packet-level, flow-level, and analytical backends, creating reusable abstractions and APIs. - Design transaction-level and cycle-approximate models of the scale-up fabric to evaluate architectural proposals prior to tape-out. - Develop theoretical roofline and analytical models to map AI/ML workload demands against fabric capabilities and identify compute-bound versus fabric-bound regimes. - Model AI/ML collective communication patterns, including AllReduce, AllGather, and ReduceScatter, alongside advanced congestion control and in-network computing features. - Evaluate fabric performance across clusters ranging from tens to thousands of GPUs, analyzing topology options, competing architectures, and technologies such as UALink, ESUN, and optical fabrics.
What you'll need
- Experience in fabric modeling, network modeling, or architectural performance analysis for high-speed interconnects. - Proficiency developing and maintaining AI/ML system simulators using packet-level, flow-level, cycle-approximate, or transaction-level modeling techniques. - Solid understanding of network traffic management, including routing, buffering, scheduling, transport protocols, and congestion control. - Knowledge of distributed AI/ML collective communication patterns such as AllReduce, AllGather, and ReduceScatter. - Experience building theoretical roofline and analytical models to characterize bandwidth, latency, and throughput bottlenecks at scale.
Skills: fabric modeling, performance analysis, AI/ML workloads, system simulators, high-speed interconnect
This role has been open 87 days — slightly above the 81-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
472
|
Median days open
81 d
|
Median salary
$240k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (472 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 472 |
| Open roles in the wider Digital Design & Verification family | 60 | 3346 · 116 employers |
| Median days open | 113 d | 81 d (+32 d vs this employer) |
| Median salary (USD postings) | — | $240k |
Skills observed across this category: fabric modeling, performance analysis, AI/ML workloads, system simulators, high-speed interconnect
Who's hiring in this category
- Qualcomm · 80 open roles · median 84 d
- NVIDIA · 54 open roles · median 68 d
- Apple · 37 open roles · median 18 d
- AMD · 36 open roles · median 75 d
- Arm Holdings · 27 open roles · median 123 d
- Micron Technology · 21 open roles · median 102 d
How we counted: 472 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.