Senior Principal Design Verification Engineer - Plano, United States
Originally posted 27 September 2026 by the employer.
Lead verification efforts for the Automotive PMIC product line.
About the role
This role involves leading verification efforts for the Automotive PMIC product line, combining expertise in mixed-signal verification methodology with leadership capabilities to mentor junior engineers and drive verification strategy.
What you'll do
- Design and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration for PMIC designs.
- Develop and implement comprehensive verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards (ISO 26262, AEC-Q200).
- Set up and optimize Gate-Level Simulation (GLS) flows, correlating with RTL simulation results.
- Lead debugging activities for complex analog blocks including switched-mode regulators, Linear Dropout (LDO) regulators, and mixed-signal interfaces.
- Conduct in-depth RTL and Gate-Level simulations, analyzing timing, power, and functional correctness across process, voltage, and temperature (PVT) corners.
- Mentor and lead junior verification engineers, defining best practices and establishing verification methodologies.
What you'll need
- MS or PhD in Electrical Engineering, Computer Engineering, or related field.
- 12+ years of experience in mixed-signal or analog circuit verification.
- Deep understanding of mixed-signal verification environment architecture and implementation.
- Hands-on experience with Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration.
- Proficiency in RTL and behavioral simulation tools (e.g., Spectre, Xcelium).
- Strong understanding of Gate-Level Simulation (GLS) flows and ability to set up and debug GLS simulations.
- Expertise debugging analog blocks (switched-mode regulators, LDO, bandgap, reference circuits) and digital RTL.
- Experience with automotive PMIC or power management IC design and verification.
- Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages.
- Solid understanding of verification methodologies: UVM, assertions, coverage-driven verification.
- Experience interfacing with multiple verification domains: functional, post-silicon, ATE test correlation.
- Leadership and mentoring experience.
This role has been open 17 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 31 | 1192 |
| Open roles in the wider Digital Design & Verification family | 84 | 3189 · 115 employers |
| Median days open | 15 d | 65 d (−50 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.