Senior Principal Analog Design Engineer
Develop power management and clocking analog IP for the Treo platform built on 65nm BCD technology.
About the role
This role contributes to the development of power management and clocking analog IP blocks for Treo-based SoC platforms built on 65nm Bipolar-CMOS-DMOS (BCD) technology.
What you'll do
- Design, simulate, and verify power management IP including LDOs, DC/DC converters, and charge pumps.
- Design and implement clocking circuits such as PLLs, DLLs, oscillators, and clock distribution networks.
- Execute schematic design, layout guidance, post-layout extraction, and corner/Monte Carlo analysis to meet specifications.
- Deliver validated analog blocks into mixed-signal and digital-on-top subsystems for SoC integration.
- Perform PVT, noise, jitter, reliability, EM/IR, and aging analysis as part of design sign-off.
- Participate in lab bring-up, silicon characterization, and post-silicon debug with validation and test engineers.
What you'll need
- 10+ years of experience in analog IC design.
- Hands-on experience designing power management and/or clocking circuits for integrated SoCs.
- Solid understanding of device physics, analog architectures, and layout-dependent effects.
- Proficiency with SPICE/AMS simulation, variability analysis, and mixed-signal co-simulation.
- Ability to work independently on assigned blocks while communicating progress and risks clearly.
Nice to have
- Experience with Verilog-A/AMS/SV RNM modeling or mixed-signal verification environments.
- Exposure to automotive or industrial reliability and functional-safety requirements.
- Interest in AI/ML-assisted design, automation, or design-space exploration.
Skills: power management IP, PLL, DC/DC, SPICE, layout extraction
More semiconductor jobs: onsemi jobs · Analog design jobs · Texas jobs
This role has been open 0 days — well below the 75-day median for Analog IC Design roles.
Analog IC Design · Power Management
|
Open roles in category
89
|
Median days open
75 d
|
Category median salary (all employers)
$181k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (89 roles · 11 employers) |
|---|---|---|
| Open roles in this specialty | 22 | 89 |
| Open roles in the wider Analog & Mixed-Signal family | 54 | 1483 · 106 employers |
| Median days open | 75 d | 75 d (same as this employer) |
| Median salary (USD postings) | — | $181k |
Skills observed across this category: power management IP, PLL, DC/DC, SPICE, layout extraction
Who's hiring in this category
- Renesas Electronics · 25 open roles · median 54 d
- onsemi (this employer) · 20 open roles · median 75 d
- Monolithic Power Systems · 10 open roles · median 171 d
- Skyworks · 8 open roles · median 7 d
- Texas Instruments · 8 open roles · median 67 d
- Analog Devices · 6 open roles · median 13 d
How we counted: 89 open Analog IC Design (Power Management) roles from 11 employers tracked in the SemiconductorJobs index, counted 3 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.