Senior NVM Digital Designer - Palo Alto, CA, United States
$178,000 - $240,000 USD yearly
Originally posted 17 August 2026 by the employer.
Design, develop, and verify the NVM controller for analog compute-in memory technology.
About the role
This role involves the design, development, and verification of NVM IP and digital controllers for Mythic’s product architecture. You will be working on the NVM controller for analog compute-in memory technology.
What you'll do
- Participate in design and verify complete IP macros for Mythic product architecture utilizing available NVM technologies.
- Contribute to NVM digital controller development.
- Design, define, and manage the interface and communications of the NVM digital controller.
- Work with NVM circuit designers on RNM, functional, and Verilog models of NVM circuits.
- Drive verification of RNM and functional models of NVM circuits.
- Participate in design reviews and improve RTL coding practices and methodologies.
What you'll need
- Ph.D. or MS degree in EE or related with 3+ years industrial experience in RTL design, microarchitecture, and architecture development.
- Hands-on experience in full chip digital simulation setup, debugging, and verification.
- Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines.
- Familiarity with timing constraints, physical design considerations, and EDA flows.
- Hands-on experience with simulation, synthesis, linting, and static timing analysis tools.
- Hands-on experience modeling circuits using Python, Verilog-A, and System Verilog Real Number Modeling.
Nice to have
- Familiar and hands-on experience on NVM (NOR / NAND / similar) voltage operation and/or programming algorithms, and timing diagram.
- Understanding of computer architecture fundamentals (pipelines, caches, coherence, memory hierarchies).
- Experience with one or more of the following subsystems: scheduling fabrics, high-performance interconnects, DMA engines, memory controllers, or datapath/control logic.
Skills: NVM digital controller, RTL design, microarchitecture, Verilog/SystemVerilog, NVM technologies
This role has been open 48 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Mythic | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 287 |
| Median days open | 48 d | 69 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: NVM digital controller, RTL design, microarchitecture, Verilog/SystemVerilog, NVM technologies
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.