Senior Mixed Signal Design Engineer

Lead the design and implementation of high speed transceivers and high frequency PLLs in deep submicron CMOS.

Originally posted 30 October 2026 by the employer. Relisted by the employer on 31 October 2026.

About the role

As a member of the Mixed Signal team, you will lead the design of CMOS high-speed interface circuits and mixed-signal circuits. Design projects include high speed transceivers and high frequency PLLs implemented in deep submicron CMOS.

What you'll do

• Lead the design, simulation, verification, and implementation of high speed interface circuits and mixed-signal circuits.
• Execute design projects encompassing high speed transceivers and high frequency PLLs.
• Supervise IC circuit and mask designers closely, providing floorplan and layout guidelines.
• Tackle challenges of circuit design in deep submicron CMOS and take designs through implementation and productization.
• Support lab characterization of silicon, including validation, debugging, and bring-up.
• Work with multi-functional teams across the development lifecycle.

What you'll need

• MS in Electrical Engineering or equivalent experience.
• 4+ years of design experience in CMOS analog / mixed-signal circuit design.
• Extensive experience in Tx, Rx, CDR, and PLL for high speed IO interfaces.
• In-depth understanding of deep submicron CMOS process and related circuit design issues.
• Solid understanding of Cadence custom design tools, circuit simulators, and timing analysis tools.
• Experience in silicon bring-up, debugging, and the use of lab instrumentation.
• Experience in Verilog, Matlab, PrimeTime, and NanoTime.

Nice to have

• Knowledge in system level timing budget, signal integrity, and power integrity.

Skills: CMOS high-speed interface circuits, high speed transceivers, high frequency PLLs, silicon validation, Cadence custom design tools, deep submicron CMOS

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