Senior Memory Technologist (ReRAM) - Gresham, OR, United States
Digital Design & SoC Architecture
Originally posted 9 September 2026 by the employer.
About the role
What you'll do
- Lead development of advanced embedded memory technologies with emphasis on ReRAM and other emerging non-volatile memory solutions.
- Define memory technology requirements including PPA targets, density goals, endurance, retention, cost, yield, and manufacturability criteria.
- Drive bitcell and array architecture evaluations, including topology selection, assist schemes, variability assessment, margin analysis, and DFM assumptions.
- Plan and execute silicon learning activities, including test-chip definition, split/DOE planning, metrology, electrical characterization, and data analysis.
- Analyze read/write behavior, endurance, retention, disturb mechanisms, variation, failure Pareto trends, and model-to-silicon correlation.
- Translate silicon learning into design rules, compact models, memory assumptions, characterization specifications, and reusable technology collateral.
What you'll need
- Master of Science or Ph.D. in Electrical Engineering, Materials Science, Physics, or Semiconductor Engineering.
- 5-10 years of relevant semiconductor industry experience in technology development, process integration, device engineering, characterization, reliability, or memory development.
- Strong understanding of semiconductor devices, wafer fabrication, process integration, and electrical characterization methodologies.
- Experience planning and analyzing DOE/split experiments, silicon learning vehicles, statistical data sets, yield learning, or technology qualification data.
- Knowledge of memory characterization methods including read, write, retention, endurance, variability, margin, and failure-mode evaluation.
- Working knowledge of device modeling, compact model correlation, SPICE/TCAD simulation concepts, or circuit-to-silicon correlation.
- Familiarity with semiconductor reliability principles and qualification methodologies such as HTOL, retention, endurance, ESD, latch-up, and failure analysis.
- Demonstrated ability to lead complex cross-functional engineering efforts from concept through silicon learning and qualification readiness.
Skills: ReRAM, bitcell, array architecture, silicon learning, memory characterization, process integration
Market context
This role has been open 25 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 287 |
| Median days open | 83 d | 69 d (+14 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: ReRAM, bitcell, array architecture, silicon learning, memory characterization, process integration
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.