Senior Memory Design Engineer - IND-Bangalore Electronic City - S1, India
Digital Design & SoC Architecture
Originally posted 16 September 2026 by the employer.
About the role
This role involves the design and development of Single/Multiport SRAM and Register file compilers.
What you'll do
- Design and develop Single/Multiport SRAM and Register file compilers in 28nm/16FF/7FF/5FF Technologies.
- Perform circuit design and simulation of key components like bitcell, WL decoder, SAMP, Column decoder, and control logic.
- Develop critical path and characterization flow for detailed margin and characterization simulations.
- Conduct Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off.
- Perform Design Tuning, Margin Analysis, and Sign-Off for complete compilers to meet yield and performance targets.
- Conduct Logic simulations and detailed timing analysis of key paths in high speed memory design, including Signal-Integrity (EM) and Power-Integrity (IR drop) analysis.
What you'll need
- Expertise in high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits.
- Experience in designing and driving one or many Memory Compilers Specifications to final release.
- Deep expertise in understanding and developing Split rail, Power gating Architecture and circuit design.
- Hands-on experience in Silicon Debug/Diagnose failures, Silicon Failures, Analysis, and fixing.
- Complete hands-on experience using Cadence/Mentor schematic/layout editor tools.
- Complete hands-on experience with Circuit simulation, MC analysis, and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave.
- Expertise in understanding layout design issues in sub nanometer regime.
- Master's Degree with 4+ years or Bachelor's Degree with 5+ years of experience.
Nice to have
- Experience in Skill/Perl/Python Scripting.
- Expertise in understanding Memory DFT.
Skills: SRAM, bitcell, Sense Amplifier, CMOS circuit design, Cadence
Market context
This role has been open 19 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 287 |
| Median days open | 51 d | 69 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: SRAM, bitcell, Sense Amplifier, CMOS circuit design, Cadence
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom (this employer) · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.