Senior Member of Technical Staff / Member of Technical Staff, DRAM Design Engineer, Next-generation HBM Architecture
$100,000 - $200,000 USD yearly
Originally posted 9 July 2026 by the employer.
About the role
As a Senior Member of Technical Staff or Member of Technical Staff, DRAM Design Engineer, you will drive the architecture and optimization of 3D-stacked, high-performance memories.
What you'll do
- Validate architectural hypotheses through schematic-level circuit design, SPICE simulation, and tradeoff analysis, establishing PPA feasibility.
- Partner with layout designers to conduct floorplanning studies.
- Collaboratively define and optimize design-for-test, design-for-yield implementation.
- Compose and maintain clear specifications and architecture documentation.
What you'll need
- Strong mixed signal design experience, including custom analog and synthesis flows.
- DRAM circuit design experience in one or more of the following focus areas: cell arrays, sense amplifiers, row/column decoders, periphery, IO, and/or power distribution.
- Engineering experience with SPICE-based tools (e.g., FineSim, HSPICE).
- Masters or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
- 8+ years of proven experience delivering DRAM-based memory designs.
Nice to have
- Experience with HBM or other novel stacked memory architectures.
- Experience in one or more scripting languages (e.g., Python, Perl) and hardware description language (e.g., Verilog).
- Strong knowledge of semiconductor device physics.
Skills: DRAM circuit architectures, AI workload requirements, SPICE simulation, HBM, semiconductor device physics
This role has been open 152 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DRAM circuit architectures, AI workload requirements, SPICE simulation, HBM, semiconductor device physics
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.