Senior Manager- SOC Verification - AZ - Chandler, United States
Originally posted 14 October 2026 by the employer.
Lead verification for 32-bit MCU products.
About the role
As the SoC Verification Manager, you will be a critical leader in our dsPIC Microcontroller Business Unit, responsible for ensuring the functional integrity of our 32-bit MCU products.
What you'll do
- Own the end-to-end verification strategy, from initial test plan development to final tape-out sign-off for multiple concurrent MCU projects.
- Lead and develop a global team of 20+ engineers, managing resource allocation, performance reviews, and technical career growth.
- Define and refine scalable, reusable testbench architectures that support both UVM simulation-based and formal-based verification flows.
- Drive the adoption of advanced techniques, including Formal Verification, Power-Aware Verification (UPF/CPF), and Hardware-Software Co-verification.
- Partner with Architecture, RTL Design, Digital Signal Processing (DSP), and Physical Design teams to resolve complex integration issues and architectural bottlenecks.
- Continuously improve verification efficiency through automation, Python/Perl scripting, and the integration of AI-driven verification tools.
What you'll need
- Bachelor of Science in Electrical Engineering or Computer Science, with strong digital design fundamentals.
- 15+ years in SoC Verification, with at least 5 years in a formal leadership or management role.
- Proven track record of successful tape-outs for 32-bit Microcontrollers; deep understanding of MCU peripherals (DMA, Timers, ADC/DAC interfaces, Security modules).
- Direct experience verifying SoCs with ARM cores (Cortex-M) and proprietary RISC-based architectures.
- Expert-level command of SystemVerilog and UVM (Universal Verification Methodology); strong hands-on experience with Formal Verification (Property Checking, Connectivity Checking) using tools like JasperGold or VC Formal.
- In-depth knowledge of AMBA bus protocols (AHB, APB, AXI); experience defining coverage-driven verification (CDV) metrics and managing massive regression suites.
Nice to have
- Strong background in Gate-Level Simulations (GLS) and power-aware verification.
- Experience with Post-Silicon Validation and its alignment with pre-silicon test plans.
- Experience with analog mixed-mode (AMS) simulations.
- Familiarity with functional safety standards (ISO 26262) for automotive MCU applications.
Skills: UVM, SystemVerilog, Formal Verification, SoC Verification, 32-bit MCU
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1187
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (1187 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 1187 |
| Open roles in the wider Digital Design & Verification family | 66 | 3192 · 115 employers |
| Median days open | 63 d | 64 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: UVM, SystemVerilog, Formal Verification, SoC Verification, 32-bit MCU
Who's hiring in this category
- Qualcomm · 103 open roles · median 42 d
- AMD · 99 open roles · median 54 d
- NVIDIA · 79 open roles · median 61 d
- Synopsys · 61 open roles · median 30 d
- SiFive · 54 open roles · median 71 d
- Cadence Design Systems · 51 open roles · median 113 d
How we counted: 1187 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.