Senior Manager, Semiconductor IC Packaging & Assembly Engineering - Batu Berendam, my, Malaysia

Originally posted 24 September 2026 by the employer.

This role supports AI/data center infrastructure power packaging applications.

About the role

This role involves managing semiconductor IC packaging assembly engineering to support sustaining engineering and high-volume manufacturing execution for advanced semiconductor packaging technologies. This position specifically supports AI/data center infrastructure power packaging applications such as Smart Power Stages, Vertical Power Stages, Power Modules, and Discrete FET packages, and wide-bandgap (WBG) technologies including SiC and GaN, DBC and AMB substrates.

What you'll do

• Support sustaining engineering across semiconductor package assembly technologies and product lines.
• Execute high-volume manufacturing improvement activities related to yield, cycle time, quality, throughput, and cost.
• Develop and maintain engineering practices for process control, defect reduction, and continuous improvement.
• Monitor assembly yield performance, trends, and corrective action progress.
• Support containment, corrective, and preventive actions for manufacturing and field quality issues.
• Support process change management for materials, equipment, tooling, flows, and sites.
• Serve as a manufacturing engineering interface for NPI-to-production transfers.
• Coordinate with global OSAT and contract manufacturing partners supporting development and production.

What you'll need

• Bachelor’s degree in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or related technical discipline.
• 15+ years of semiconductor manufacturing and packaging engineering experience with strong exposure to IC assembly operations, package development, qualification, and NPI-to-HVM transfers.
• 3+ years of experience leading technical projects, mentoring engineers, or managing small engineering teams in semiconductor manufacturing environments.
• Strong expertise in semiconductor package assembly and related processes including FET wafer metallization processing, thin die processing, wirebond, clip attach, flip chip, solder die attach, reflow, molding, package singulation, package buffing/grinding, die embedding, and SMT.
• Deep understanding of semiconductor manufacturing yield analysis, SPC, DOE, reliability, process control methodologies, package/process qualification methods, and statistical analysis tools.
• Experience working with global OSAT partners and outsourced manufacturing ecosystems, including benchmarking, selection, qualification, and ongoing technical management of subcontractors and contract manufacturers.
• Demonstrated experience supporting successful NPI-to-HVM product ramp execution.
• Strong knowledge of semiconductor quality systems, change management, and qualification methodologies.

Nice to have

• Master’s degree or PhD in Engineering or related field.
• Experience with advanced packaging technologies for power packages, such as SiP/modules, multi-chip modules, Smart Power Stages, Vertical Power Stages, Power Modules, and Discrete FET packages.
• Wafer-level packaging and substrate-level packaging design and technology knowledge.
• Wide-bandgap packaging knowledge for SiC and GaN dies including knowledge of DBC, AMB, and advanced interconnect technologies.
• 2.5D/3D packaging, fan-out, embedded die, and heterogeneous integration.
• Familiarity with automotive, AI/data center infrastructure power, high-performance computing, power semiconductor, and wide-bandgap product manufacturing requirements.
• Knowledge of reliability standards including JEDEC, IPC, and customer qualification requirements.