Senior IP Design Verification Engineer - XBAR IP - India, Bengaluru
Verification, Validation & Test
Originally posted 6 October 2026 by the employer.
About the role
This role involves verifying the design and implementation of memory subsystem units using advanced verification methodologies. The focus is on XBAR IP.
What you'll do
- Verify the ASIC design, architecture, and micro-architecture of memory sub-systems/units.
- Define the verification scope and develop the verification infrastructure.
- Create test plans, tests, and verification infrastructure for complex IPs/sub-systems.
- Build reusable bus functional models, monitors, checkers, and scoreboards following coverage driven verification methodology.
- Apply advanced verification methodologies like SV/UVM.
- Perform functional coverage driven verification closure.
- Collaborate with architects, designers, and pre and post silicon verification teams.
What you'll need
- 4+ years of relevant experience.
- Experience in verification of complex IPs/units and sub-systems.
- Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
- Expertise in Verilog.
- Knowledge in SystemVerilog or similar HVL / UVM or VMM.
Market context
This role has been open 0 days — well below the 61-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1203
|
Median days open
61 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1203 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 79 | 1203 |
| Open roles in the wider Digital Design & Verification family | 237 | 3179 · 113 employers |
| Median days open | 60 d | 61 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Who's hiring in this category
- AMD · 104 open roles · median 47 d
- Qualcomm · 102 open roles · median 45 d
- NVIDIA (this employer) · 75 open roles · median 61 d
- Synopsys · 70 open roles · median 29 d
- SiFive · 56 open roles · median 60 d
- Cadence Design Systems · 52 open roles · median 113 d
How we counted: 1203 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 7 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.