Senior High-Speed IO Validation Engineer
$136,000 - $258,750 USD yearly
Validate high-speed interfaces including PCIe, NVLink, C2C, and CXL across protocol, link, and physical layers on GPU and CPU platforms.
Originally posted 30 October 2026 by the employer. Relisted by the employer on 31 October 2026.
About the role
This role drives end-to-end HSIO validation across GPU, CPU, and high-performance computing platforms from initial bring-up to full-scale production.
What you'll do
- Own end-to-end HSIO validation of hardware products, including test plan development, automation, coverage metrics, test execution, bug resolution, and release to production.
- Validate high-speed interfaces such as PCIe, NVLink, C2C (Chip-to-Chip), Ethernet, USB, DP, HDMI, and CXL across the protocol, link, and physical layers.
- Bring up new hardware platforms and debug board- and system-level issues across logic/circuit design, board design, simulation, diagnostics, firmware, and software teams.
- Review board schematics, PCB layouts, and BOMs to evaluate components and ensure interoperability in complex interconnect topologies.
- Drive signal integrity characterization, link tuning, and margin analysis to confirm specification compliance and workload performance.
- Define and execute functionality test coverage from link bring-up through stress testing, including link training, error handling, power management, and interoperability.
What you'll need
- BS or higher in EE, CE, or equivalent experience.
- 3+ years of post-silicon HSIO validation or system bring-up experience.
- Ability to work on site in a hardware lab environment 5 days a week at NVIDIA HQ.
- Understanding of at least one high-speed interface protocol (PCIe, NVLink, C2C, Ethernet, USB, CXL, Display) or SerDes/signal integrity at the PHY level, including link training and system-level operation.
- Hands-on experience with lab equipment including high-bandwidth DSOs, BERTs, protocol/logic analyzers, protocol exercisers, and TDR.
- System-level debug skills on complex hardware platforms.
Skills: high-speed interfaces, PCIe, NVLink, CXL, Ethernet, protocol, link, physical layers, signal integrity characterization, lab equipment
More semiconductor jobs: NVIDIA jobs · Signal integrity jobs · California jobs
This role has been open 144 days — well above the 72-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
246
|
Median days open
72 d
|
Category median salary (all employers)
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (246 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 246 |
| Open roles in the wider Analog & Mixed-Signal family | 61 | 1553 · 106 employers |
| Median days open | 205 d | 72 d (+133 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: high-speed interfaces, PCIe, NVLink, CXL, Ethernet, protocol, link, physical layers, signal integrity characterization, lab equipment
Who's hiring in this category
- Synopsys · 34 open roles · median 40 d
- AMD · 26 open roles · median 46 d
- Cadence Design Systems · 21 open roles · median 144 d
- Qualcomm · 19 open roles · median 73 d
- Micron Technology · 13 open roles · median 45 d
- Apple · 9 open roles · median 28 d
How we counted: 246 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.