Senior FPGA Architect (Compute Test, North Reading)
$154,900 - $247,800 USD yearly
Originally posted 24 September 2026 by the employer.
Architect and deliver high-performance FPGA-based solutions for Teradyne's Compute Test platforms.
About the role
This role involves architecting and delivering high-performance FPGA-based solutions at the heart of test platforms, working at the intersection of FPGA design, board-level hardware, and system architecture. It focuses on advanced test solutions for high-performance SoCs and accelerators powering modern compute and AI systems.
What you'll do
- Lead FPGA design from architecture through implementation and bring-up, including requirements definition, trade-off analysis, timing closure, resource optimization, and performance tuning.
- Develop high-performance FPGA solutions involving complex interfaces and subsystem integration, along with automation and debug tools using TCL and Python.
- Collaborate with hardware, software, systems, and design verification teams to deliver cohesive system-level solutions.
- Build and execute validation strategies, including lab bring-up, debug, and root cause analysis using JTAG and lab instrumentation.
- Partner on PCB and system design decisions that affect FPGA performance and integration.
What you'll need
- 8+ years of hands-on experience in FPGA design and development.
- Deep expertise in Verilog/SystemVerilog for design and debugging.
- Proven experience with AMD (Xilinx) and/or Intel FPGA toolchains, including synthesis, implementation, and timing closure.
- Strong understanding of digital design fundamentals and the ability to interpret schematics.
- Experience with high-speed interfaces such as PCIe, DDR, SerDes, or similar technologies, and with protocols such as AXI4, USB, I2C, and SPI.
- Scripting proficiency in TCL and Python for automation and tooling, plus experience with version control systems and collaborative development workflows.
Nice to have
- Experience with SystemVerilog-based verification methodologies such as UVM.
- Experience with FPGA SoCs and embedded processor subsystems.
- Experience with ATE or measurement equipment design.
- Experience with signal integrity, high-speed serial interfaces, and transceivers.
- Experience with DDR, HBM, and Flash memory technologies.
- Experience with AI tools for engineering design.
This role has been open 22 days — well below the 60-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
102
|
Median days open
60 d
|
Median salary
$162k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (102 roles · 26 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 102 |
| Median days open | 70 d | 60 d (+10 d vs this employer) |
| Median salary (USD postings) | — | $162k |
Who's hiring in this category
- Altera · 30 open roles · median 59 d
- AMD · 12 open roles · median 50 d
- Teradyne (this employer) · 10 open roles · median 69 d
- Qualcomm · 8 open roles · median 41 d
- Microchip Technology · 6 open roles · median 92 d
- Infineon Technologies · 4 open roles · median 37 d
How we counted: 102 open FPGA Design (RTL Design) roles from 26 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.