Senior Formal Verification Engineer (CH-64001149) - Austin, Texas, United States
Originally posted 21 January 2026 by the employer.
About the role
Cirrus Logic is seeking an experienced Formal Verification Engineer in Austin, TX to build and leverage both formal and dynamic verification environments for critical areas of audio and mixed-signal devices.
What you'll do
- Develop and enhance formal methodologies to be rolled out to the wider design and verification teams, and investigate new capabilities based on formal verification. - Mentor and coach engineers in formal verification techniques, application of formal methodologies, and adherence to defined methodology practices. - Develop test plans and verification methodologies to verify microarchitecture and design. - Perform failure analysis and resolution, coverage analysis, and coverage population. - Implement and improve functional verification environments across IP and module-level designs.
What you'll need
- Master's degree in Electrical or Computer Engineering with 8+ years or PhD in Electrical or Computer Engineering with 5+ years of formal verification experience. - Expertise in designing and implementing formal verification environments for complex IP/module-level designs, with experience in property-based model-checking. - Expertise in formal property languages, including SVA knowledge. - Proficiency in System Verilog, UVM, or equivalent verification methodologies. - Familiarity with scripting languages such as Python, Perl, TCL, or Bash. - Knowledge of signal processing, analog, and digital design fundamentals.
Skills: formal verification, SystemVerilog, SVA, model-checking, verification methodologies
This role has been open 220 days — well above the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cirrus Logic | All employers we track in this specialty (1254 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 1254 |
| Open roles in the wider Digital Design & Verification family | 29 | 3346 · 116 employers |
| Median days open | 217 d | 66 d (+151 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: formal verification, SystemVerilog, SVA, model-checking, verification methodologies
Who's hiring in this category
- Qualcomm · 118 open roles · median 45 d
- AMD · 92 open roles · median 55 d
- NVIDIA · 91 open roles · median 65 d
- Synopsys · 65 open roles · median 41 d
- SiFive · 55 open roles · median 83 d
- Cadence Design Systems · 52 open roles · median 125 d
How we counted: 1254 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.