Senior Engineer - Design Verification - Ahmedabad, India
Originally posted 28 September 2026 by the employer.
About the role
This role involves driving the verification of a cache-coherent interconnect subsystem in high-performance SoCs. It focuses on coherent interconnect and related subsystem behavior.
What you'll do
- Understand coherent interconnect architecture and create verification strategies and test plans.
- Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
- Verify subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths.
- Define and execute directed and constrained-random tests to expose corner cases.
- Analyze failures, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
- Write functional coverage, analyze coverage results, and close coverage holes.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 5+ years of relevant experience in IP, subsystem, or SoC functional verification.
- Strong hands-on experience with SystemVerilog and UVM-based verification.
- Solid understanding of cache-coherent systems, on-chip interconnects, and memory-subsystem behavior.
- Experience creating test plans, building testbenches, writing assertions, analyzing coverage, and debugging complex design issues.
- Experience verifying protocol behavior such as ordering, backpressure, buffering, arbitration, flow control, and error handling.
Nice to have
- Direct experience verifying coherent interconnect, NoC, cache, or memory-subsystem functionality.
- Experience with subsystem integration and protocol interactions across multiple interfaces or bridge paths.
- Familiarity with industry protocols such as AXI, CHI, ACE, CXL, UCIe.
- Familiarity with scripting and automation using Python or similar languages.
- Experience with formal verification, performance-oriented verification, or emulation / FPGA-assisted debug.
- Experience contributing reusable infrastructure or methodology improvements.
Skills: UVM-based verification, SystemVerilog, coherent interconnect, cache-coherent systems, coverage models
This role has been open 29 days — well below the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiFive | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 56 | 1268 |
| Open roles in the wider Digital Design & Verification family | 87 | 3328 · 116 employers |
| Median days open | 80 d | 67 d (+13 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM-based verification, SystemVerilog, coherent interconnect, cache-coherent systems, coverage models
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive (this employer) · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.