Senior Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU
$138,000 - $206,000 USD yearly
Originally posted 26 August 2026 by the employer.
Work on RISC-V microarchitecture and performance for emerging data center and agentic AI workloads.
About the role
What you'll do
- Collaborate with Staff and Principal Engineers, owning a microarchitectural domain from idea proposal through implementation and validation.
- Participate in design implementation and validation using AI-driven design methodologies.
- Run architectural simulations and performance models, and analyze results such as IPC, CPI stacks, latency, and throughput.
- Identify performance bottlenecks and optimization opportunities across the front-end, mid-end, and back-end.
- Characterize workloads and benchmarks to understand performance behavior and architectural opportunities.
- Contribute to patents and technical publications based on architectural research.
What you'll need
- Master’s degree in Computer Architecture, Computer Engineering, or a related field with 3+ years of experience, or a PhD in Computer Architecture, Computer Engineering, or a related field.
- 1+ years of experience in CPU microarchitecture or performance engineering.
- Strong understanding of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems.
- Hands-on experience with architectural simulators such as gem5.
- Proficiency in C/C++ and Python.
Nice to have
- Experience with RISC-V, ARM, or x86 CPU cores, or with GPU/NPU vector unit design.
- Experience with or interest in AI-driven or agentic design workflows.
- Understanding of execution patterns and characteristics of agentic AI workloads.
- Domain-specific experience in the front-end, mid-end, or back-end areas.
- Experience with PPA trade-off analysis.
- Experience with CPU tape-out or silicon validation.
- Experience with patents or technical publications related to CPU.
Skills: CPU architectures, microarchitectural research, performance modeling, AI-driven design methodologies, silicon validation
This role has been open 50 days — well below the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
470
|
Median days open
79 d
|
Median salary
$235k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (470 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 470 |
| Open roles in the wider Digital Design & Verification family | 13 | 3183 · 115 employers |
| Median days open | 46 d | 79 d (−33 d vs this employer) |
| Median salary (USD postings) | — | $235k |
Skills observed across this category: CPU architectures, microarchitectural research, performance modeling, AI-driven design methodologies, silicon validation
Who's hiring in this category
- Qualcomm · 72 open roles · median 86 d
- NVIDIA · 56 open roles · median 68 d
- Apple · 39 open roles · median 9 d
- AMD · 35 open roles · median 64 d
- Arm Holdings · 27 open roles · median 112 d
- NXP Semiconductors · 21 open roles · median 114 d
How we counted: 470 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.
Samsung Semiconductor
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