Senior Emulation Performance Methodology & Debug Engineer
$121,800 - $182,600 USD yearly
Originally posted 21 September 2026 by the employer.
Qualcomm's Emulation Team is part of the central SoC digital hardware organization responsible for the overall development and support of SoC pre-silicon platforms.
About the role
This role involves the overall development and support of SoC pre-silicon platforms, focusing on emulation performance methodology and debug.
What you'll do
- Design, develop, and deploy uniform global methodologies for emulation build generation and debug across FPGA-based emulation platforms.
- Bring-up new FPGA emulation/prototyping hardware and software.
- Debug low-level software and hardware issues.
- Validate and debug digital circuits.
- Collaborate across sites and engage with vendors.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field.
- Experience with Emulation Platforms (FPGA Prototyping, Veloce, Palladium).
- Experience with Emulation tools (Synthesis, Place and Route, Constraints, Clocking, Timing Closure).
- Expertise in Verilog / SystemVerilog.
- Experience with C programming.
- Proficiency in Python, TCL scripting.
- Experience with FPGA Expertise: Xilinx/Intel FPGAs, Tools, and timing closure techniques.
- Experience with debug tools including JTAG and kernel debuggers.
- Understanding of CPU and SoC architectures, including SoC building blocks (interconnects, power management, PMIC, NoC, peripherals).
Nice to have
- 5 years of experience working in emulation and silicon environments.
- Experience in pre-silicon prototyping for new SoC designs, including pre-silicon enablement and bring-up.
- Basic understanding of power and performance.
Skills: Emulation Platforms, FPGA Prototyping, FPGA emulation, timing closure, SystemVerilog, JTAG
This role has been open 20 days — well below the 53-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
104
|
Median days open
53 d
|
Median salary
$162k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (104 roles · 27 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 104 |
| Median days open | 36 d | 53 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $162k |
Skills observed across this category: Emulation Platforms, FPGA Prototyping, FPGA emulation, timing closure, SystemVerilog, JTAG
Who's hiring in this category
- Altera · 30 open roles · median 53 d
- AMD · 11 open roles · median 48 d
- Teradyne · 10 open roles · median 63 d
- Qualcomm (this employer) · 8 open roles · median 35 d
- Microchip Technology · 6 open roles · median 86 d
- Infineon Technologies · 4 open roles · median 31 d
How we counted: 104 open FPGA Design (RTL Design) roles from 27 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.