Senior Director Verification SOC Engineering
Originally posted 9 November 2026 by the employer.
About the role
This role leads SoC Verification within the System Solutions Group (SSG), developing and implementing system design solutions using Synopsys EDA tools and IP for customer service projects. The position involves managing a team of SoC/Subsystem/IP verification engineers across verification planning, testbench and VIP integration, regressions, gate-level simulations, and emulation.
What you'll do
- Lead, build, and manage a team of 15+ SoC and subsystem verification engineers across multiple sites for customer engagements.
- Work directly with customers to understand design requirements, estimate effort, schedule, and cost, and define verification scope and activities.
- Drive verification plan development, testbench and VIP integration, regressions, gate-level simulations, and emulation support across complex IP blocks, subsystems, and full SoC top levels.
- Collaborate with architects and RTL designers to draft detailed test specifications, test plans, and finalize design tradeoffs, performance verification, and interconnects.
- Partner with internal Synopsys teams, including Business Unit Applications Engineers and Sales, to deploy verification tool and IP solutions.
- Review verification results and regression reports to improve execution efficiency and deliverable quality.
What you'll need
- B.E/B.Tech/M.E/M.Tech in Electronics with 20+ years of experience in the SoC verification domain.
- Technical expertise in pre-silicon SoC/subsystem verification, including UVM, coverage analysis, verification plan creation, and debugging.
- Hands-on experience with verification tools such as VCS, waveform analyzers, and third-party VIP integration (such as Synopsys VIPs).
- Knowledge of protocols such as PCIe, Ethernet, USB, DDR, and/or processor, interconnect, and debug architecture.
- Demonstrated experience planning and managing verification execution for complex SoCs, subsystems, and IPs across consumer, automotive, HPC, or AI domains.
- Deep understanding of ASIC flows, design concepts, and cross-functional technical stakeholders.
Skills: UVM, SoC Verification, VCS, VIP, pre-silicon
More semiconductor jobs: Synopsys jobs · Verification engineer jobs · Austin jobs
First seen in our index 0 days ago, well below the 62-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1339
|
Median days since first seen
62 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (1339 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 75 | 1339 |
| Open roles in the wider Digital Design & Verification family | 193 | 3526 · 120 employers |
| Median days since first seen | 56 d | 62 d (+6 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: UVM, SoC Verification, VCS, VIP, pre-silicon
Who's hiring in this category
- Qualcomm · 120 open roles · median 51 d
- Apple · 108 open roles · median 15 d
- NVIDIA · 108 open roles · median 74 d
- AMD · 79 open roles · median 70 d
- Synopsys (this employer) · 73 open roles · median 56 d
- SiFive · 57 open roles · median 70 d
How we counted: 1339 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 12 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.