Senior Digital Verification Engineer - Bangalore, Karnataka, India
Originally posted 5 October 2026 by the employer.
About the role
This role involves developing and executing comprehensive verification plans for subsystem and SoC-level designs, utilizing System Verilog and UVM.
What you'll do
- Develop and execute comprehensive verification plans for subsystem and SoC-level designs.
- Develop reusable verification environments using System Verilog and UVM.
- Create constrained-random, directed, and scenario-based test cases.
- Develop scoreboards, monitors, protocol checkers, assertions (SVA), and coverage models.
- Analyze and debug RTL and gate-level simulation failures for timing and functional signoff.
- Analyze, debug, and enhance C/C++ golden reference models for functional verification.
- Execute and debug fault injection simulations to validate functional safety requirements and fault handling mechanisms.
What you'll need
- Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
- 5-7 years of hands-on experience in Digital/ASIC/SoC Verification.
- Strong expertise in System Verilog.
- Strong expertise in UVM.
- Familiarity with industry-standard simulators such as Xcelium and Questa.
- Verification experience with I2C, AHB/APB, and MIPI protocols.
Nice to have
- Exposure to Gate-Level Simulation (GLS).
Skills: Digital/ASIC/SoC Verification, System Verilog, UVM, Xcelium, Questa, I2C, AHB/APB, MIPI
This role has been open 22 days — well below the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 1268 |
| Open roles in the wider Digital Design & Verification family | 59 | 3328 · 116 employers |
| Median days open | 78 d | 67 d (+11 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Digital/ASIC/SoC Verification, System Verilog, UVM, Xcelium, Questa, I2C, AHB/APB, MIPI
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.