Senior Digital Verification Engineer - Bangalore, Karnataka, India
Originally posted 5 October 2026 by the employer.
About the role
This role involves developing and executing comprehensive verification plans for subsystem and SoC-level designs, utilizing System Verilog and UVM.
What you'll do
- Develop and execute comprehensive verification plans for subsystem and SoC-level designs.
- Develop reusable verification environments using System Verilog and UVM.
- Create constrained-random, directed, and scenario-based test cases.
- Develop scoreboards, monitors, protocol checkers, assertions (SVA), and coverage models.
- Analyze and debug RTL and gate-level simulation failures for timing and functional signoff.
- Analyze, debug, and enhance C/C++ golden reference models for functional verification.
- Execute and debug fault injection simulations to validate functional safety requirements and fault handling mechanisms.
What you'll need
- Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
- 5-7 years of hands-on experience in Digital/ASIC/SoC Verification.
- Strong expertise in System Verilog.
- Strong expertise in UVM.
- Familiarity with industry-standard simulators such as Xcelium and Questa.
- Verification experience with I2C, AHB/APB, and MIPI protocols.
Nice to have
- Exposure to Gate-Level Simulation (GLS).
Skills: Digital/ASIC/SoC Verification, System Verilog, UVM, Xcelium, Questa, I2C, AHB/APB, MIPI
This role has been open 3 days — well below the 62-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1206
|
Median days open
62 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (1206 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 1206 |
| Open roles in the wider Digital Design & Verification family | 57 | 3184 · 113 employers |
| Median days open | 68 d | 62 d (+6 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Digital/ASIC/SoC Verification, System Verilog, UVM, Xcelium, Questa, I2C, AHB/APB, MIPI
Who's hiring in this category
- AMD · 106 open roles · median 48 d
- Qualcomm · 104 open roles · median 43 d
- NVIDIA · 79 open roles · median 61 d
- Synopsys · 64 open roles · median 30 d
- SiFive · 55 open roles · median 65 d
- Cadence Design Systems · 52 open roles · median 108 d
How we counted: 1206 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 8 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.