Senior Digital Engineer - Chandler, United States
Originally posted 9 July 2026 by the employer. Relisted by the employer on 22 October 2026.
Architect and integrate low-power digital circuits for mixed-signal data conversion and power management products.
About the role
As a Senior Digital Engineer at Renesas Electronics, you will be responsible for designing power and area-optimized digital circuits for complex mixed-signal applications in Chandler, AZ. The scope focuses on architecting and integrating low-power digital circuits for mixed-signal data conversion and power management products.
What you'll do
- Architect, design, and integrate digital RTL that meets timing, area, and power specifications across micro-architecture, design partitioning, and synthesis. - Integrate designs at the top level, execute block and top-level simulations, and assist with top-level testbench debug. - Participate across the mixed-signal flow, including generating timing constraints, timing analysis, LINT, CDC, RDC, and UPF. - Collaborate with the P&R team to guide layout closure for timing, area, and power requirements. - Partner with analog and digital verification teams on test scenarios, RTL and gate-level simulations, and AMS, SystemVerilog, or Verilog-real behavioral models. - Support DFT strategy and test case development, participate in design reviews, and assist with silicon evaluation.
What you'll need
- Over 5 years of digital design experience in wireless handheld, data conversion, or power management applications. - Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline. - Fluency in Verilog / SystemVerilog RTL for digital CMOS circuit design. - Strong understanding of ASIC design methodology, Lint, CDC, and RDC tools. - Demonstrated experience debugging RTL and gate-level simulations, alongside block-level and chip-level verification techniques. - Willingness to travel domestically or internationally on short notice.
Nice to have
- Experience with mixed-signal design methodologies. - Experience developing design constraints and hand-off to P&R, STA, and timing closure. - Experience with low-power design techniques, including clock and power gating (UPF), as well as power analysis and optimization. - Experience with advanced verification methodologies (UVM). - Experience with industry-standard protocols such as AMBA or I2C.
Skills: Verilog, SystemVerilog, RTL, ASIC design methodology, Mixed-signal design flow
This role has been open 105 days — well above the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1070
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (1070 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 23 | 1070 |
| Open roles in the wider Digital Design & Verification family | 82 | 3298 · 115 employers |
| Median days open | 59 d | 62 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Verilog, SystemVerilog, RTL, ASIC design methodology, Mixed-signal design flow
Who's hiring in this category
- Qualcomm · 153 open roles · median 58 d
- Synopsys · 87 open roles · median 35 d
- AMD · 76 open roles · median 40 d
- Analog Devices · 49 open roles · median 51 d
- NXP Semiconductors · 42 open roles · median 90 d
- NVIDIA · 41 open roles · median 62 d
How we counted: 1070 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.