Senior Digital Engineer - Bengaluru, India
Originally posted 7 July 2026 by the employer — open 75 days.
About the role
This role involves developing micro-architecture and front-end digital designs for various power management ASICs from concept to silicon with minimal supervision.
What you'll do
- Develop micro-architecture and front-end digital design deliverables.
- Lead optimized digital blocks design meeting functional and low power constraints.
- Define Digital/Analog boundaries and digital design scope for Power Management ICs.
- Define micro-architectures and sub-blocks for ICs to ensure optimized Digital design, RTL design, and Gate level netlist.
- Handle Clock Domain Crossing across multiple clock domains seamlessly and glitch-free.
- Lead or collaborate on Logic Synthesis, Formal verification, Power estimation, and STA.
- Support DFT strategy and implementation.
- Interface with Placement and Route team for digital hand-off and post layout verification.
- Perform physical silicon device area and power evaluation.
- Author high-quality documentation for digital blocks.
What you'll need
- 3-6 years of experience in Logic design, micro-architecture, or RTL coding.
- Hands-on experience with Power product design, synthesis, and timing analysis for complex Digital Circuits.
- Experience in Verilog/System-Verilog.
- Experience working in semiconductor, ideally PMIC, with a focus on mixed signal integrated circuits.
- Hands-on experience developing block and top-level timing constraints for STA and Placement and Route sign off.
- Understanding of design constraints and synthesis scripts.
- Experience with OTP, MTP, Efuse read/writes, controller design, and data bus handling.
- Experience with Register read/write and Trimming of Analog parts/functions.
- Familiarity with one or more Power Chip Communication I/Ps and protocols (e.g., I2C, PMBUS, SPI).
- Experience with silicon debugs and root cause analysis of issues.
- Degree level qualification in Electronics Engineering.
Skills: power management ASICs, digital blocks design, RTL design, Power product design, mixed signal integrated circuits, PMIC
This role has been open 75 days — slightly above the 71-day median for Power Electronics roles.
Power Electronics · Power Management
|
Open roles in category
71
|
Median days open
71 d
|
Median salary
$169k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (71 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 71 |
| Open roles in the wider Analog & Mixed-Signal family | 87 | 1337 · 105 employers |
| Median days open | 75 d | 71 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $169k |
Skills observed across this category: power management ASICs, digital blocks design, RTL design, Power product design, mixed signal integrated circuits, PMIC
Who's hiring in this category
- Renesas Electronics (this employer) · 15 open roles · median 75 d
- Qualcomm · 8 open roles · median 38 d
- Analog Devices · 6 open roles · median 81 d
- Monolithic Power Systems · 6 open roles · median 184 d
- AMD · 5 open roles · median 89 d
- Infineon Technologies · 5 open roles · median 72 d
How we counted: 71 open Power Electronics (Power Management) roles from 25 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.