Senior Digital Design Engineer - Toronto, Ontario, Canada
$139,500 - $155,000 CAD yearly
Originally posted 10 September 2026 by the employer.
Design high-performance connectivity silicon for rack-scale AI infrastructure, focusing on PCIe and Ethernet controllers.
About the role
As a Senior Digital Design Engineer, you will design and integrate high-performance connectivity silicon for AI infrastructure. You will contribute across architecture, micro-architecture, RTL implementation, synthesis, timing closure, and IP integration for PCIe and Ethernet controllers, bridges, switches, and related SerDes interfaces.
What you'll do
- Develop micro-architecture and implement synthesizable RTL for high-performance PCIe or Ethernet controllers, bridges, switches, and SerDes-related IP.
- Translate architecture and protocol requirements into scalable designs using SystemVerilog and Verilog.
- Own block-level and full-chip design deliverables from specification through implementation and GDS handoff.
- Drive synthesis, timing analysis, timing closure, clock-domain crossing, lint, and design-quality reviews.
- Support gate-level simulation, emulation, and pre-silicon and post-silicon design implementation activities.
- Collaborate with verification and system teams to assess verification completeness, debug design issues, and close implementation gaps.
What you'll need
- Experience developing micro-architecture and synthesizable RTL for PCIe or Ethernet controllers, bridges, switches, and SerDes-related IP.
- Proficiency in SystemVerilog and Verilog.
- Experience with block-level and full-chip design deliverables through implementation and GDS handoff.
- Experience with designs at advanced process nodes of 16 nm or smaller, including PCIe Gen 6/7, UALink, or UCI-based connectivity.
- Experience integrating controller, SerDes, processor, peripheral, and other IP with RTL, physical design, DFT, verification, and firmware teams.
- Experience with synthesis, timing analysis, timing closure, clock-domain crossing, lint, and design-quality reviews.
- Experience with gate-level simulation, emulation, and pre-silicon and post-silicon design implementation activities.
- Experience with top-level integration, floor-planning discussions, PAD planning, and DFT implementation.
- Experience collaborating with verification and system teams to assess verification completeness and debug design issues.
- Experience partnering with firmware and embedded software teams to define and validate hardware-software interfaces.
- Experience using Synopsys and Cadence design and analysis tools.
- Scripting proficiency in Python or Perl.
This role has been open 46 days — well below the 66-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1081
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1081 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 29 | 1081 |
| Open roles in the wider Digital Design & Verification family | 61 | 3328 · 116 employers |
| Median days open | 46 d | 66 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 158 open roles · median 63 d
- Synopsys · 86 open roles · median 40 d
- AMD · 77 open roles · median 45 d
- Analog Devices · 49 open roles · median 56 d
- NXP Semiconductors · 44 open roles · median 100 d
- NVIDIA · 37 open roles · median 52 d
How we counted: 1081 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.