Senior DFT - Silicon Validation Engineer - CA, Santa Clara, United States
$168,000 - $310,500 USD yearly
Originally posted 8 June 2026 by the employer. Relisted by the employer on 14 August 2026.
About the role
As a Senior DFT - Silicon Validation Engineer on NVIDIA's Design-for-Test Engineering team, you will drive silicon validation and DFT methodologies to support post-silicon bring-up and characterization.
What you'll do
- Drive end-to-end DFT architecture and methodologies to support post-silicon bring-up and characterization. - Collaborate across multi-functional teams to define test strategies for ATE across the product roadmap. - Lead early silicon validation for complex SoC designs, including planning from architecture through development. - Perform chip validation on ATE, debug test content, and analyze silicon behavior across operating conditions. - Identify failure root causes and work with multi-functional teams to drive production ramp and yield.
What you'll need
- BSEE (or equivalent experience) with 8+ years, MSEE with 5+ years, or PhD with 3+ years in DFT or related domains. - Expertise in silicon debug, bring-up, and productization of DFT features. - Experience in pre-silicon validation for various DFT features. - Demonstrated experience driving yield ramp and waste reduction across products. - Scripting and programming skills in Perl, Python, or Tcl.
Nice to have
- Track record of implementing advanced DFT methodologies in semiconductor technologies. - Knowledge of high-speed protocols and semiconductor process technology. - Knowledge of industry-standard DFT tools and software.
Skills: DFT architecture, scan test plans, memory BIST, ATPG, fault simulation
This role has been open 136 days — well above the 63-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
248
|
Median days open
63 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (248 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 23 | 248 |
| Open roles in the wider Digital Design & Verification family | 225 | 3322 · 115 employers |
| Median days open | 41 d | 63 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DFT architecture, scan test plans, memory BIST, ATPG, fault simulation
Who's hiring in this category
- AMD · 38 open roles · median 45 d
- Qualcomm · 26 open roles · median 73 d
- NVIDIA (this employer) · 23 open roles · median 42 d
- NXP Semiconductors · 19 open roles · median 47 d
- Synopsys · 15 open roles · median 30 d
- Intel Corporation · 11 open roles · median 53 d
How we counted: 248 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.