Senior DFT Engineer

Own design-for-test for AI compute ASIC and SoC designs at Mueon in Hillsboro, Oregon: scan, compression, ATPG and coverage closure from RTL through tapeout.

Originally posted November 13, 2026 by the employer.

About the role

Mueon is a Hillsboro, Oregon semiconductor company building compute, memory and interconnect technology for AI computing platforms. As a Senior DFT (Design-for-Test) Engineer on the RTL Design team, you will own testability for ASIC and SoC designs from RTL through tapeout: testability checks, scan insertion and compression, ATPG pattern generation, and fault coverage closure.

You will work closely with the RTL, physical design, STA and product/test engineering teams.

What you will do

• Check designs for testability at RTL and gate level, and fix DRC violations such as uncontrollable clocks and resets, combinational loops and non-scannable flops.
• Define the DFT architecture, including scan, compression, test modes, test clocking and on-chip clock controllers (OCC).
• Insert scan chains and scan compression, balancing chain lengths and handling multiple clock domains and lock-up latches.
• Generate and optimize ATPG patterns with Synopsys TetraMAX (TestMAX ATPG) for stuck-at, transition delay, path delay and IDDQ faults.
• Analyze fault and test coverage, debug untestable and undetected faults, and add test points to close coverage gaps.
• Run zero-delay and SDF-annotated gate-level simulations of ATPG patterns and debug mismatches.
• Support STA with shift and capture test-mode timing constraints, and work with physical design on scan chain reordering.
• Implement and verify MBIST, LBIST, JTAG (IEEE 1149.1) and boundary scan, and IEEE 1500/1687 (IJTAG) where needed.
• Support silicon bring-up on ATE, including STIL/WGL pattern conversion, failure diagnosis and yield analysis.

Required qualifications

• B.S. or M.S. in Electrical or Computer Engineering, or a related field.
• 3+ years of hands-on DFT experience on ASIC or SoC projects; at least one tapeout strongly preferred.
• Hands-on Synopsys TetraMAX / TestMAX ATPG: tool setup, DRC, pattern generation, and coverage reporting and analysis.
• Scan insertion with Synopsys DFT Compiler / TestMAX DFT or similar tools.
• Fault models (stuck-at, transition, path delay, bridging) and the difference between fault coverage and test coverage.
• Scan compression (for example DFTMAX or EDT) and at-speed testing with OCC.
• Working knowledge of Verilog/SystemVerilog, synthesis flows and STA basics.
• Tcl scripting, plus Python or Perl, to automate flows.
• Gate-level simulators such as VCS, Xcelium or Questa.

Preferred qualifications

• Siemens Tessent (TestKompress, MBIST) or Cadence Modus.
• MBIST and memory repair, LBIST, and hierarchical or core-based DFT.
• Silicon debug and yield learning with volume diagnosis tools.
• Low-power DFT across multiple power domains, with UPF awareness.
• Advanced process nodes (7nm and below) and cell-aware or small-delay-defect ATPG.

How you work

• Strong analytical and debugging skills, comfortable working through complex tool reports.
• Clear communication across design, verification, physical design and test teams.
• Ownership of DFT deliverables on a tapeout schedule.

About Mueon

Mueon is building an Exponential Computing Platform: foundational silicon technology for computing and AI.

Location: Hillsboro, Oregon, United States

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