Senior DFT Design Engineer - San Jose, California, United States
$187,000 - $270,700 USD yearly
Originally posted 13 October 2026 by the employer.
About the role
This role involves developing DFT architectures and implementing test solutions for Altera's FPGA, processor, DSP, SERDES, IO, and 2.5D/3D multi-die packaging products.
What you'll do
- Define and implement DFT architectures and specifications for FPGA, processors, DSP, SERDES, IO, and multi-die designs.
- Perform test logic insertion, ATPG pattern generation, and pre-silicon validation for manufacturability and quality.
- Collaborate with IP and integration design teams to align DFT features with design functionality and timing.
- Partner with test development teams to support silicon bring-up, debug, and production readiness.
- Contribute to DFT methodology and automation flows to enhance scalability and efficiency.
- Ensure manufacturability goals are met, including test coverage, test cost optimization, yield improvement, and debug support.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 10+ years of industry experience, or Master’s degree with 8+ years of industry experience.
- 8+ years of experience in DFT design and verification at both RTL and gate level.
- Experience in EDA tools such as synthesis and scan insertion tools, ATPG tools, simulation and debug tools, STA tools.
- Design automation experience and proficiency in scripting languages such as Perl/TCL.
Nice to have
- Experience with test compression, BIST (MBIST/LBIST), and advanced fault models.
- Prior experience with 2.5D/3D multi-die designs and high-speed IO/SerDes DFT.
This role has been open 2 days — well below the 56-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
250
|
Median days open
56 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Altera | All employers we track in this specialty (250 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 250 |
| Open roles in the wider Digital Design & Verification family | 24 | 3190 · 115 employers |
| Median days open | 6 d | 56 d (−50 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Who's hiring in this category
- AMD · 40 open roles · median 41 d
- NVIDIA · 25 open roles · median 41 d
- Qualcomm · 24 open roles · median 101 d
- NXP Semiconductors · 18 open roles · median 63 d
- Synopsys · 13 open roles · median 23 d
- Micron Technology · 11 open roles · median 54 d
How we counted: 250 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.