Senior Development Test Engineer — Pre & Post-Silicon Software Test, Validation and Characterization - Bengaluru, India
This role involves validating high-speed die-to-die (UCIe) interconnects.
About the role
This role involves the end-to-end testing, characterization, and failure analysis strategy for complex multi-die packages, covering high-speed die-to-die (UCIe) interconnects, Power Delivery Networks (PDN/PMIC), Platform Management Controllers (PMC), and PCIe/CXL subsystems.
What you'll do
- Define development test strategies, coverage targets, content architecture, and traceability from architectural requirements to validation evidence.
- Write low-level C and Python test suites, including bare-metal exercisers, traffic generators, stress patterns, and custom firmware drivers/hooks.
- Build robust test frameworks featuring instrument control, automated sequencing, structured result capture, and Hardware-in-the-Loop (HIL) CI/CD integration.
- Develop lab-to-ATE correlation test suites and drive handoffs to Product & Test Engineering (PTE).
- Build minimally invasive fault-injection hardware/software infrastructure.
- Execute rigorous error campaigns targeting CRC retries, lane degradation/repair, sideband timeouts, PCIe AER, DMA/IOMMU translation faults, and PMIC reset conditions.
What you'll need
- 8–10+ years in post-silicon validation, system software testing, silicon bring-up, or development test for complex SoCs / ASICs / GPUs.
- Advanced proficiency in C and Python for low-level bare-metal test content, hardware abstraction, and automation frameworks.
- Proven experience with Shmoo plotting PVT corner testing, jitter/margin analysis, and guard-band definition.
- Hands-on experience building or executing error-injection and recovery validation campaigns on production silicon.
- Fluency with oscilloscopes, protocol analyzers (PCIe/CXL), logic analyzers, BERTs, thermal chambers, controllable power supplies, and JTAG debuggers.
- Practical, protocol-level understanding of high-speed serial interfaces (PCIe, CXL, or UCIe) and control buses (I2C, SPI, UART, PMBus, SMBus).
- Solid grasp of system power delivery, including sequencing, PMIC telemetry, DVFS, voltage regulation, and protection trip limits.
- Competency with toolchains (Git, CMake, GCC/Clang, CI pipelines) and statistics/data analysis over test populations.
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
- AI coding and automation tool usage.
This role has been open 0 days — well below the 54-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
114
|
Median days open
54 d
|
Median salary
$164k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | TYLsemi | All employers we track in this specialty (114 roles · 26 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 114 |
| Open roles in the wider Silicon Validation & Test family | 2 | 2061 · 112 employers |
| Median days open | 0 d | 54 d (−54 d vs this employer) |
| Median salary (USD postings) | — | $164k |
Who's hiring in this category
- NVIDIA · 17 open roles · median 55 d
- Qualcomm · 16 open roles · median 37 d
- AMD · 15 open roles · median 41 d
- Graphcore · 9 open roles · median 97 d
- Amazon · 8 open roles · median 16 d
- Altera · 6 open roles · median 27 d
How we counted: 114 open Post-Silicon Validation (Design Verification) roles from 26 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.