Senior Design Verification Engineer - San Jose, CA, United States
$168,000 - $336,000 USD yearly
Originally posted 7 June 2026 by the employer. Relisted by the employer on 17 October 2026.
About the role
As a Senior Design Verification Engineer, you will develop and support the tools, automation, and flows used to design, verify, and tape out advanced memory products. You will work closely with design, layout, verification, and process teams in areas including layout automation, physical verification, circuit simulation, and digital implementation.
What you'll do
- Develop, enhance, and debug CAD tools, automation, and flows for custom IC design, layout, simulation, and verification. - Integrate, evaluate, and qualify in-house and commercial EDA tools in production environments. - Partner with design, layout, verification, and process teams to resolve workflow and tool-integration challenges. - Apply AI/ML and agentic AI to CAD automation, debugging, and user support. - Identify gaps in current tools and flows, evaluating EDA industry offerings to improve quality, performance, and efficiency. - Provide training, documentation, and production support to end users while contributing to CAD methodology roadmaps.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent. - 5+ years of industry experience in CAD, EDA, or semiconductor design. - Experience developing or supporting EDA tools and flows in at least one area: custom layout, physical verification, circuit simulation, or digital implementation. - Experience with IC design CAD tools for schematic capture, layout, simulation, or verification. - Proficiency in Python and at least one additional language such as SKILL, Tcl, Perl, C, or C++, plus Linux/Unix and shell scripting. - Solid CMOS and VLSI fundamentals, with practical debugging skills across global teams.
Nice to have
- Experience with Cadence Virtuoso and SKILL, including layout automation or parameterized cell (PCell) development. - Experience with Calibre design rule checking (DRC) and layout versus schematic (LVS) flows, or rule-deck development in SVRF. - Experience with circuit simulators such as Spectre, HSPICE, FineSim, PrimeSim, VCS, or Xcelium. - Experience with RTL-to-GDS tools such as Fusion Compiler, Innovus, PrimeTime, or Formality. - Experience with parasitic extraction tools such as StarRC or Quantus. - Experience applying AI/ML, large language models, or agentic AI to engineering workflows. - Experience with source control, automated testing, and release management. - Knowledge of DRAM, HBM, NAND, or emerging memory development.
Skills: UVM System Verilog, ASIC simulation tools, verification methods, test plans, coverage closure, SoC plus CPU emulation
This role has been open 137 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (1254 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 44 | 1254 |
| Open roles in the wider Digital Design & Verification family | 105 | 3322 · 115 employers |
| Median days open | 103 d | 64 d (+39 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM System Verilog, ASIC simulation tools, verification methods, test plans, coverage closure, SoC plus CPU emulation
Who's hiring in this category
- Qualcomm · 120 open roles · median 43 d
- AMD · 94 open roles · median 53 d
- NVIDIA · 84 open roles · median 65 d
- Synopsys · 67 open roles · median 39 d
- SiFive · 55 open roles · median 81 d
- Cadence Design Systems · 52 open roles · median 123 d
How we counted: 1254 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.