Senior Design Verification Engineer - Brno, South Moravia, Czech Republic
Originally posted 3 September 2026 by the employer.
Join onsemi’s new and growing RISC-V division.
About the role
This role involves participating in the complete verification process for configurable and customizable RISC-V CPU IP, from defining verification plans and strategies to implementation, debugging, metric-driven verification closure, tape-out, and delivery of reviewable evidence.
What you'll do
- Define and execute verification plans for RISC-V CPU features, configurations, and custom extensions.
- Translate architecture, product, safety, and security requirements into measurable verification objectives and closure criteria.
- Develop reusable SystemVerilog/UVM environments, assertions, checkers, reference models, coverage models, and regression infrastructure.
- Verify ISA behavior, privilege modes, exceptions, interrupts, memory interfaces, debug functionality, configurations, and custom instruction interactions.
- Combine simulation and advanced formal techniques to address complex control logic and high-risk corner cases.
- Apply metric-driven verification to measure progress, identify quality gaps, and support sign-off decisions.
What you'll need
- Strong experience in CPU, SoC, or complex reusable digital IP verification.
- Advanced knowledge of SystemVerilog, UVM, assertions, functional coverage, and verification debugging.
- Experience with verification planning, metric-driven execution, coverage analysis, and quality-based closure.
- Understanding of processor concepts such as pipelines, privilege levels, exceptions, interrupts, memory access, and debug.
- Experience with formal verification or strong motivation to develop advanced formal verification expertise.
- Ability to translate technical requirements into measurable verification objectives and reviewable evidence.
Skills: SystemVerilog, UVM, formal verification, RISC-V CPU, functional coverage, metric-driven verification
This role has been open 54 days — well below the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 1268 |
| Open roles in the wider Digital Design & Verification family | 59 | 3328 · 116 employers |
| Median days open | 78 d | 67 d (+11 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog, UVM, formal verification, RISC-V CPU, functional coverage, metric-driven verification
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.