Senior Design Verification Engineer (BO - 01) - Chandler, Arizona, United States
Originally posted 16 February 2026 by the employer.
About the role
Participate in all aspects of verification for complete mixed-signal IC developments within the silicon design verification team. You will work on complex verification systems, contribute to verification methodology improvements, and collaborate with digital/analog designers, applications engineers, and manufacturing test.
What you'll do
- Perform verification planning, coverage analysis, and population. - Develop testbenches using UVM methodologies and execute digital/mixed-signal modeling. - Implement functional verification of mixed-signal ASICs and handle failure analysis and resolution. - Develop directed and constraint-random test generation, along with gate-simulations. - Provide regression debug support and develop verification flows and infrastructure.
What you'll need
- MS or PhD in Electrical Engineering or Computer Engineering. - At least 5+ years of experience in silicon design or verification. - Background with HDLs (e.g. Verilog, VHDL). - Background with HVLs (e.g. SystemVerilog/UVM, OVM, AVM, Vera).
Nice to have
- Experience supporting both pre-silicon verification and post-silicon validation efforts with digital/analog designers, applications engineers, and manufacturing test. - Knowledge of signal processing and Verilog Assertions. - Ability to create, evaluate, debug, and improve verification processes. - Ability to mentor junior engineers in verification methodology.
Skills: verification planning, Testbench development, UVM methodologies, functional verification, mixed-signal ASICs
This role has been open 220 days — well above the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cirrus Logic | All employers we track in this specialty (1254 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 1254 |
| Open roles in the wider Digital Design & Verification family | 29 | 3346 · 116 employers |
| Median days open | 217 d | 66 d (+151 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: verification planning, Testbench development, UVM methodologies, functional verification, mixed-signal ASICs
Who's hiring in this category
- Qualcomm · 118 open roles · median 45 d
- AMD · 92 open roles · median 55 d
- NVIDIA · 91 open roles · median 65 d
- Synopsys · 65 open roles · median 41 d
- SiFive · 55 open roles · median 83 d
- Cadence Design Systems · 52 open roles · median 125 d
How we counted: 1254 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.