This role involves developing IP for Automotive, Industrial & Medical products.
Originally posted 1 August 2026 by the employer.
About the role
This role involves the design verification of complex mixed-signal IPs. This includes familiarity with analog blocks such as DACs, ADCs, PLL, and wireless interfaces.
What you'll do
- Define verification strategies and detailed verification plans for blocks and systems
- Coordinate verification activities in project teams
- Develop System Verilog/UVM environments for blocks and top-level SoCs
- Debug functional errors in RTL
- Participate in verification methodology improvement activities
What you'll need
- BS/MS in Electrical Engineering or related technical field
- Minimum 3 years of digital verification experience
- Solid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage
- In-depth knowledge and proven experience in UVM methodologies
- Experience with constrained random driven verification, assertion-based verification, test environment architecture & creation, regression management, and coverage collection
Skills: System Verilog, UVM, RTL, functional coverage, constrained random verification
More semiconductor jobs: onsemi jobs · Verification engineer jobs · India jobs
First seen in our index 104 days ago, well above the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1395
|
Median days since first seen
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (1395 roles · 100 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 1395 |
| Open roles in the wider Digital Design & Verification family | 53 | 3606 · 122 employers |
| Median days since first seen | 85 d | 59 d (−26 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: System Verilog, UVM, RTL, functional coverage, constrained random verification
Who's hiring in this category
- Qualcomm · 129 open roles · median 52 d
- NVIDIA · 109 open roles · median 73 d
- Apple · 107 open roles · median 16 d
- AMD · 82 open roles · median 63 d
- Synopsys · 80 open roles · median 57 d
- SiFive · 57 open roles · median 71 d
How we counted: 1395 open Design Verification (Design Verification) roles from 100 employers tracked in the SemiconductorJobs index, counted 13 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.