Senior Design Verification Engineer
$190,610 - $269,100 USD yearly
Verify coherent chassis and interconnect IP, including AMBA CHI and CXL architectures, for SoC and chiplet systems.
Originally posted 11 November 2026 by the employer.
About the role
As a Senior Design Verification Engineer on the Unified Intel Chassis (UIC) team, you will verify coherent, non-coherent, and I/O-coherent systems across interconnects, caches, memory subsystems, and chassis functions. The team develops chassis and interconnect IP along with a configurable generator for SoCs and chiplets.
What you'll do
- Own verification plans for chassis and interconnect IP, prioritize functional and integration risks, and drive features from initial bring-up through signoff.
- Build reusable environments, reference models, and checkers for data integrity, ordering, address translation, access permissions, interrupt routing and delivery, and forward progress.
- Combine simulation, formal properties, and targeted experiments to discover bugs and review assumptions, checker completeness, and coverage gaps.
- Collaborate with design and verification engineers to define interface contracts, share VIP and assertions, and debug interactions across data paths, clock and power transitions, reset sequences, and debug and trace functions.
- Develop configuration-driven regressions and AI-assisted workflows for coding, property development, and debug with independent checks across supported configurations.
- Mentor engineers through code and testplan reviews, communicate remaining risks, and establish evidence for verification closure.
What you'll need
- BS/MS in Electrical Engineering, Computer Science, or a related field with 10+ years of relevant experience in design verification, spanning IP DV, subsystem, and SoC-level verification.
- Hands-on experience verifying high-performance interconnects and memory subsystems, including coherent, non-coherent, and I/O-coherent operation, cache coherency, memory consistency, transaction ordering, virtual memory, IOMMUs, and interrupt controllers.
- Experience with MESI/MOESI-based coherency mechanisms and protocols such as AMBA CHI, CXL, or comparable architectures.
- SystemVerilog/UVM and assertion-based verification skills, with practical experience applying formal verification alongside simulation.
- Programming and debugging skills in SystemVerilog and Python or C/C++, with the ability to read RTL, build independent reference models and checkers, and develop test automation.
Nice to have
- Experience with configurable interconnect generators, generated testbenches, and verification across topology, parameter, and multi-die configurations.
- Experience with formal abstraction and proof decomposition, or emulation-based validation of system workloads.
- Experience verifying clocking, power management, reset, debug, trace, RAS, security isolation, or QoS interactions at subsystem level.
- Knowledge of cache hierarchies, home nodes, duplicate-tag structures, snoop filters, memory controllers, and how their interactions affect correctness and performance.
- Experience building and evaluating AI-assisted engineering workflows, including checks for incorrect generated code, properties, or specification interpretations.
Skills: SystemVerilog, UVM, AMBA CHI, formal verification, coherency
More semiconductor jobs: Intel Corporation jobs · Verification engineer jobs
First seen in our index 2 days ago, well below the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1412
|
Median days since first seen
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (1412 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 47 | 1412 |
| Open roles in the wider Digital Design & Verification family | 114 | 3617 · 122 employers |
| Median days since first seen | 29 d | 59 d (+30 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: SystemVerilog, UVM, AMBA CHI, formal verification, coherency
Who's hiring in this category
- Qualcomm · 138 open roles · median 52 d
- NVIDIA · 109 open roles · median 74 d
- Apple · 107 open roles · median 17 d
- Synopsys · 90 open roles · median 53 d
- AMD · 81 open roles · median 65 d
- SiFive · 57 open roles · median 72 d
How we counted: 1412 open Design Verification (Design Verification) roles from 101 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.