Senior Design Verification Engineer
$190,610 - $269,100 USD yearly
Verify networking IPs and SoCs implementing RDMA protocols including RoCEv2, iWARP, and InfiniBand.
Originally posted 10 November 2026 by the employer.
About the role
As an IP Design Verification Engineer, you will ensure the functionality and reliability of intellectual property (IP) designs across architecture, design, and verification groups. The role focuses on verifying networking IPs and SoCs implementing RDMA protocols and reliable transport architectures.
What you'll do
- Develop and execute comprehensive verification plans to ensure IP logic meets microarchitecture specifications.
- Create and maintain test benches and verification environments to achieve high coverage and reliability.
- Perform system simulations to verify designs, analyze power and timing, and identify bugs in the presilicon environment.
- Debug verification issues by replicating, root-causing, and implementing corrective measures for failing tests.
- Collaborate with architects, RTL developers, and physical design teams to enhance verification methodologies for complex features.
- Maintain and improve existing verification infrastructure, tools, and methodologies, contributing to technical flow methodologies (TFMs).
What you'll need
- Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field with 9+ years of experience in IP functional verification (or 6+ years with a Master's degree, or 4+ years with a PhD).
- Hands-on experience building verification environments using SystemVerilog and UVM.
- Expertise in RTL design and debugging using industry-standard tools and methodologies.
- Hands-on experience verifying networking IPs/SoCs implementing RDMA (RoCEv2, iWARP, InfiniBand) or comparable reliable transport protocols (e.g., Ultra Ethernet Transport, TCP offload), including features such as QP/connection state, retransmission, packet ordering, and congestion control.
Nice to have
- Familiarity with scripting languages, such as Python or Perl, to automate verification tasks.
Skills: SystemVerilog, UVM, RDMA, RTL, functional verification
More semiconductor jobs: Intel Corporation jobs · Verification engineer jobs
First seen in our index 3 days ago, well below the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1412
|
Median days since first seen
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (1412 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 47 | 1412 |
| Open roles in the wider Digital Design & Verification family | 114 | 3617 · 122 employers |
| Median days since first seen | 29 d | 59 d (+30 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: SystemVerilog, UVM, RDMA, RTL, functional verification
Who's hiring in this category
- Qualcomm · 138 open roles · median 52 d
- NVIDIA · 109 open roles · median 74 d
- Apple · 107 open roles · median 17 d
- Synopsys · 90 open roles · median 53 d
- AMD · 81 open roles · median 65 d
- SiFive · 57 open roles · median 72 d
How we counted: 1412 open Design Verification (Design Verification) roles from 101 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.