Senior Design Engineer - San Jose, CA, United States
$116,000 - $246,000 USD yearly
Originally posted 8 May 2026 by the employer. Relisted by the employer on 8 October 2026.
About the role
As a Senior Design Engineer in the NVE Design Engineering Core group at Micron Technology, you will design and analyze core and mixed circuits for memory products. The work focuses on developing array waveforms, wordline and bitline path architectures, and schematics for NAND Flash memory.
What you'll do
- Develop array waveforms with detailed timing and biasing conditions of array signals using NAND Flash memory read, program, and erase algorithms. - Collaborate with Firmware, Analog, and Design validation teams during the implementation of waveforms. - Plan wordline and bitline path architectures according to area, performance, and power specifications, and integrate circuit blocks into the chip plan. - Perform die size cost and benefits analysis of new array circuits and algorithms, working across teams to evaluate and improve NAND power consumption. - Generate Xpath, Ypath, and Array schematics, run block-level, subsystem, and full-chip simulations using SPICE simulators, and oversee layout implementation. - Develop and maintain Python-based automation and AI-assisted utilities with EDA environments for corner execution, regression runs, and automated documentation.
What you'll need
- MS in Electrical Engineering (PhD preferred). - 4+ years of relevant NAND design experience. - Strong fundamentals in semiconductor and device physics and analog/mixed-signal circuit design. - Understanding of semiconductor reliability issues including CHC, NBTI, stress, snapback, Electromigration (EM), and IR analysis. - Experience with circuit verification and optimization, layout planning, parasitic extractions, and guiding layout. - Coding skills in Python and experience working with structured data (CSV/JSON/SQLite) and version control.
Nice to have
- Knowledge of analog and digital simulators such as HSPICE, Fast SPICE, and Verilog. - Familiarity with Cadence design tools and LVS/DRC tools. - Experience with Bash or Tcl scripting. - Familiarity with Linux/UNIX environments.
Skills: NAND analog and mixed-signal circuits, compute-in-memory, ADC architectures, sensing, amplification, bias generation, semiconductor and device physics, Python-based AI utilities
This role has been open 222 days — well above the 71-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
309
|
Median days open
71 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (309 roles · 31 employers) |
|---|---|---|
| Open roles in this specialty | 157 | 309 |
| Median days open | 91 d | 71 d (+20 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: NAND analog and mixed-signal circuits, compute-in-memory, ADC architectures, sensing, amplification, bias generation, semiconductor and device physics, Python-based AI utilities
Who's hiring in this category
- Micron Technology (this employer) · 157 open roles · median 91 d
- Synopsys · 30 open roles · median 67 d
- Qualcomm · 19 open roles · median 88 d
- Broadcom · 17 open roles · median 68 d
- SanDisk · 17 open roles · median 54 d
- NVIDIA · 7 open roles · median 34 d
How we counted: 309 open Memory Design (Memory Design) roles from 31 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.