Senior Design Engineer, Coherent High Speed Interconnect
Architect and design NVLINK-C2C coherent interconnects for mobile SoCs, GPUs, DPUs, and custom silicon chiplets.
Originally posted 30 October 2026 by the employer.
About the role
NVIDIA is looking for a Senior Design Engineer to work on the architecture and design of high-speed coherent interconnects (NVLINK-C2C) for mobile SoCs and GPUs. The role involves designing chiplet-based interconnect solutions that link GPUs, DPUs, and CPUs with custom silicon.
What you'll do
- Architect and design high-speed coherent interconnects (NVLINK-C2C) for mobile SoCs and GPUs.
- Collaborate with architects, external partners, software engineers, and circuit designers to deliver coherent interconnect implementations.
- Support chiplet-based integrated products that coherently interconnect GPUs, DPUs, and CPUs with custom silicon.
What you'll need
- BS or equivalent experience in Electrical Engineering, Computer Engineering, or a related degree, plus 8+ years of relevant design experience.
- Strong working knowledge of Verilog or SystemVerilog.
- Experience and knowledge in architecture, RTL design, performance analysis, and power optimization.
- Understanding of or experience with link layer stacks, including the data link layer and physical layer.
- Experience with the physical layer of interconnects such as Memory (DDR, LPDDR), PCIe, or SerDes.
- Knowledge of industry standard interconnect protocols such as PCIe, CXL, AXI, or CHI.
Skills: coherent interconnects, NVLINK-C2C, chiplets, high speed interconnects, integrated products
More semiconductor jobs: NVIDIA jobs · Signal integrity jobs · California jobs
This role has been open 203 days — well above the 72-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
246
|
Median days open
72 d
|
Category median salary (all employers)
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (246 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 246 |
| Open roles in the wider Analog & Mixed-Signal family | 61 | 1553 · 106 employers |
| Median days open | 205 d | 72 d (+133 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: coherent interconnects, NVLINK-C2C, chiplets, high speed interconnects, integrated products
Who's hiring in this category
- Synopsys · 34 open roles · median 40 d
- AMD · 26 open roles · median 46 d
- Cadence Design Systems · 21 open roles · median 144 d
- Qualcomm · 19 open roles · median 73 d
- Micron Technology · 13 open roles · median 45 d
- Apple · 9 open roles · median 28 d
How we counted: 246 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.