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Altera

Senior Backend Design Automation Engineer — New Process Node Enablement - San Jose, California, United States

Altera San Jose, California, United States Full-time 2 months ago
Physical Design & EDA

$149,100 - $215,925 USD yearly

Originally posted 26 August 2026 by the employer.

About the role

This role involves senior ownership of backend design automation flows, focusing on bringing up and supporting the design environment for new process nodes. The position entails transforming raw PDK deliveries into a functional design environment by intercepting PDK and Foundation IP from the foundry, updating flow scripts, and configuring EDA tools.

What you'll do

  • Own the end-to-end bring-up, qualification, and production deployment of Backend design automation flows for new process nodes and technology releases.
  • Partner with design leads, domain representatives, and technology enablement teams to translate new-node requirements into scalable Back-End methodologies and flows.
  • Integrate and qualify new PDKs, standard-cell libraries, Foundation IP, and other technology collateral, updating EDA tool configurations, flow scripts, and supporting infrastructure.
  • Develop, maintain, and execute comprehensive regression test cases to validate Back-End flow functionality.
  • Support Back-End design teams through production use and tape-out, including flow deployment, debug, user support, training, and documentation.
  • Contribute to the modernization and consolidation of Back-End construction, verification, and analysis flows within a unified design automation environment.
  • Evaluate and apply AI/ML techniques and AI-assisted development tools to improve flow development, regression analysis, debug, runtime/resource optimization, and knowledge capture.

What you'll need

  • Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related technical field, with 8+ years of professional experience in Back-End IC design or design automation.
  • 8+ years of professional experience owning, developing, or supporting production Back-End design flows, including PDK installation and setup, custom design construction, circuit simulation, cell characterization, physical verification (DRC/LVS), RC extraction, static timing analysis, IR/EM, or power analysis.
  • 8+ years of professional experience working with semiconductor process technologies, including bringing up or migrating design environments to new process nodes or technology releases.
  • 8+ years of professional experience using industry-standard Back-End EDA tools from Synopsys, Cadence, and/or Siemens.
  • 8+ years of professional experience developing and maintaining software and automation for semiconductor design flows, including Python, Tcl, shell scripting, with a strong understanding of algorithms and data structures.
  • 8+ years of professional experience working in Linux/UNIX environments with distributed compute infrastructure and job schedulers.

Skills: backend design automation, new process node enablement, PDK integration, EDA tool configurations, physical verification

Market context

This role has been open 50 days — well below the 78-day median for EDA/CAD Engineering roles.

EDA/CAD Engineering · EDA Tools

Open roles in category
688
Median days open
78 d
Median salary
$195k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Altera compares in EDA/CAD Engineering hiring
Metric Altera All employers we track in this specialty (688 roles · 74 employers)
Open roles in this specialty 9 688
Open roles in the wider Physical Implementation family 28 1459 · 108 employers
Median days open 50 d 78 d (−28 d vs this employer)
Median salary (USD postings) — $195k

Skills observed across this category: backend design automation, new process node enablement, PDK integration, EDA tool configurations, physical verification

Who's hiring in this category

  • Cadence Design Systems · 153 open roles · median 168 d
  • Synopsys · 65 open roles · median 38 d
  • Micron Technology · 44 open roles · median 80 d
  • Qualcomm · 41 open roles · median 66 d
  • NVIDIA · 39 open roles · median 79 d
  • GlobalFoundries · 33 open roles · median 35 d

How we counted: 688 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.

Apply now
San Jose, California, United States
On-site
Full-time
$149,100 - $215,925 USD yearly
2 months ago

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