Senior ATE Test Engineer - San Jose, California, United States
$135,500 - $170,000 USD yearly
Originally posted 31 August 2026 by the employer.
About the role
This role involves developing and supporting complex mixed-signal silicon SoC products, leading ATE Test solutions.
What you'll do
- Develop and oversee SoC test strategy.
- Define and implement ATE programs.
- Own the product from design, initial samples through high volume production ramp.
- Implement ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
- Develop DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
- Perform silicon/ATE bring-up, bench-ATE correlation, and debug.
What you'll need
- Bachelor’s in EE.
- ≥2 year experience releasing complex SoC/silicon products to high volume manufacturing.
- Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB.
- Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.
- Familiarity with high-speed load board design techniques.
- Expertise in production test of high speed SerDes operating at 16Gbps and higher.
- Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG.
- Skilled in ATE programming.
- Experience with lab equipment including protocol analyzers and oscilloscopes.
- Experience with using Advantest 93k ATE platform.
- Proficiency in, at least, one modern programming language such as C/C++, Python.
Nice to have
- Fluent in data processing using high level programming languages.
- Experience in running External loopback at wafer sort.
- Familiarity with modern databases.
This role has been open 28 days — slightly above the 24-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
481
|
Median days open
24 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (481 roles · 72 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 481 |
| Open roles in the wider Silicon Validation & Test family | 18 | 2181 · 111 employers |
| Median days open | 30 d | 24 d (+6 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Teradyne · 54 open roles · median 11 d
- Infineon Technologies · 37 open roles · median 33 d
- Renesas Electronics · 33 open roles · median 29 d
- AMD · 27 open roles · median 26 d
- Qualcomm · 26 open roles · median 14 d
- Micron Technology · 25 open roles · median 29 d
How we counted: 481 open Silicon Test Engineering (DFT Test) roles from 72 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.