Senior AI Performance Architect - Raleigh, North Carolina, United States of America
$126,700 - $217,900 USD yearly
Originally posted 18 January 2026 by the employer.
About the role
Qualcomm is seeking an AI Accelerator Architecture Engineer to define hardware enhancements, performance models, and architectures for AI training systems. The role spans flexible computational blocks, memory technologies, and scale-out/scale-up interconnects for large-scale AI workloads.
What you'll do
- Analyze current accelerator and GPU architectures and architect hardware enhancements for training AI models. - Design computational blocks supporting dense and sparse GEMM/GEMV across floating point, fixed point, and microscaling formats from 1-bit to 32-bit precision. - Architect scale-out and scale-up topologies, including switches, NoCs, and co-design with communication collectives. - Co-design hardware with software and generative AI (LLM) requirements. - Define performance models to evaluate architecture proposals and deliver pre-silicon performance projections for ML training workloads. - Evaluate performance, area, and power trade-offs for future hardware and software ML algorithms, including SOC memory and bus impacts.
What you'll need
- Bachelor's degree in Computer Science, Engineering, Information Systems, or related field with 2+ years of hardware, software, or systems engineering experience (or Master's with 1+ year, or PhD). - 3 years of hardware engineering experience defining the architecture of GPUs or accelerators used for training AI models. - Knowledge of NVIDIA and AMD GPU architectures and capabilities. - Knowledge of LLM architectures and their hardware requirements.
Nice to have
- Knowledge of computer architecture, digital circuits, and hardware simulators. - Knowledge of communication protocols, Network-on-Chip (NoC) designs in SoC environments, and memory technologies used in AI systems. - Experience with high-level hardware modeling to extract performance and power estimates. - Familiarity with AI training systems such as NVIDIA DGX and NVL72. - Experience training and fine-tuning LLMs using distributed frameworks such as DeepSpeed or FSDP. - Knowledge of ML frameworks including TensorFlow and PyTorch, as well as model classes such as CNNs and RNNs. - Ability to code in C and Python.
Skills: ML network design, AI training systems, accelerator architectures, LLM architectures, performance models, hardware architecture
This role has been open 200 days — well above the 87-day median for AI/ML Hardware Engineering roles.
AI/ML Hardware Engineering · AI ML Hardware
|
Open roles in category
506
|
Median days open
87 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (506 roles · 77 employers) |
|---|---|---|
| Open roles in this specialty | 104 | 506 |
| Open roles in the wider Software, Firmware & Systems family | 735 | 6250 · 144 employers |
| Median days open | 116 d | 87 d (+29 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: ML network design, AI training systems, accelerator architectures, LLM architectures, performance models, hardware architecture
Who's hiring in this category
- Qualcomm (this employer) · 105 open roles · median 116 d
- NVIDIA · 89 open roles · median 58 d
- AMD · 33 open roles · median 107 d
- Micron Technology · 26 open roles · median 59 d
- Mobileye · 20 open roles · median 85 d
- Analog Devices · 18 open roles · median 43 d
How we counted: 506 open AI/ML Hardware Engineering (AI ML Hardware) roles from 77 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.