Semiconductor Principal Design Engineer - Tokyo, Japan
Originally posted 21 July 2026 by the employer.
About the role
This Principal Design Engineer contributes to the design, layout, and optimization of datapath circuits for NAND flash memory.
What you'll do
- Design and optimize TSV interface circuits connecting memory die to logic die, including Rx/Tx circuits.
- Define and implement signal integrity requirements for the TSV channel, including eye margin, crosstalk, and noise budget analysis.
- Architect the data path from the page buffer through data line sense amplifier, redundancy logic, and bus driver to the TSV output interface.
- Develop clocking and synchronization strategies for the highly parallel internal bus, including wave pipeline design and clock distribution.
- Develop and execute functional verification plan for TSV interface and internal parallel bus including full chip circuit simulation and Verilog regression.
- Support post-silicon validation, debug, and correlation activities, identifying schematic edits and driving tape-out revisions.
What you'll need
- BS or MS in Electrical Engineering with 8+ years of relevant experience in memory circuit design, preferably in DRAM, NAND, or other high-density memory technologies.
- Experience with TSV interface circuit design or high-speed memory interface design (NV-LPDDR4, DDR4/5, LPDDR5/6, HBM3/3E/4), including timing analysis, parasitic modeling, and signal integrity.
- Advanced knowledge and understanding of highly parallel bus performance, power, and area optimization, including clock distribution and skew management.
- Experience managing complex circuit design projects spanning multiple functional blocks and cross-functional teams.
Nice to have
- Hands-on experience in utilizing AI to improve quality of design and efficiency.
- Experience on chip level PDN optimization.
- Comprehensive understanding on CMOS device and device reliability.
- Comprehensive understanding on CMOS BSIM model and CMOS target for high-speed IO operation.
- Experience with signal/power integrity, power delivery network design, physical design.
Skills: TSV interface circuits, memory die to logic die, Rx/Tx circuit, HBM like highly parallel bus architecture, post-silicon validation
This role has been open 180 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: TSV interface circuits, memory die to logic die, Rx/Tx circuit, HBM like highly parallel bus architecture, post-silicon validation
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.